soha

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  1. Hi @jpeyron, Yes I checked the link but it seems there is no tutorial on how to manipulate these device registers... I've also submitted a request to the Linaro community but haven't received any reply... Anyway, if we regard the coresight component as a normal hardware device, there might be (I guess) some common solution for my case?
  2. Thanks @jpeyron . I'm looking forward to it.
  3. I have a Ubuntu Linux (4.6 kernel) running on a Zedboard, which is based on an ARM architecture. The architecture comes with a hardware module called Coresight, which enables HW-based program tracing. In my setup, the Coresight component is registered at physical address 0xf889c000. I want to configure the component through the device register etmcr, whose offset is 0x0. I tried to run devmem2 (a program helps manipulate physical memory via mmap) as a root to write some custom value to this register. The mmap threw no error, the write succeeded since the immediate readback value was the expect
  4. Hi @jpeyron, Thanks for your reply. I think the reason why I cannot get it work previously is that I didn't connect the clock input to the trace I/O. I thought there is an intrinsic clock signal in the PS that drives the trace module by default. Currently, I still cannot see my output in the COM monitoring terminal on my PC. Probably there is some driver-related problem. Unfortunately, I don't have o-scope by my side now so I am not able to physically touch the pin. In any case, I believe the FPGA-side work should be just as what you suggested. Thanks for your help! Best, soha
  5. Hi @jpeyron, Thanks for your reply. I think the trace port from CoreSight is quite similar as other I/O peripheral like UART, SPI, etc. and can be mapped through either MIO or EMIO, as the block diagram below shows. I know JE Pmod is the PS-side Pmod and I think this is why you suggest to use it. But it seems that some of the JE Pmod pins has been occupied by some other peripheral and I think if you map the I/O peripheral through EMIO, you can only map it to PL-side Pmod, right? That's why I'm trying to use PL-side Pmod. What actually confused me is what the requirement is to m
  6. Hi, I have loaded a Linaro Ubuntu on the Zedboard using Vivado 2016.2 and I want to extract the CoreSight trace data off the board. By applying the same idea suggested in the link http://blog.idv-tech.com/2014/03/22/howto-export-zynq-peripheralsi2c-spi-uart-and-etc-to-pmod-connectors-of-zedboard-using-vivado-2013-4/ , I enabled CoreSight component in the block customization of the Zynq PS, mapped its IO to EMIO, made the TRACE_0 external, and changed my .XDC file to map the 8-bit output data to the JA1 PMOD data pins. However, I'm not sure with my next step. When I powered on my board and
  7. Hi Jpeyron, Thanks for your reply and I don't know why I didn't get email notification when you update so I kind of missed it. I guess your concern is valid and I just have a very quick question (and it might be stupid but I just want to make sure). The question is: Whether my peripheral communicates with the memory through AXI bus or DMA, my peripheral can only write its own allocated address space. Is this correct? For example, if I create a CIP and it is mapped to a base address 0x10000000 with a 4K memory space, I can only read/write this space, right? There is no way to read/wri
  8. Hi, I have a Zedboard and I have loaded a Linux OS on it. I'm wondering how I can implement an AXI master custom IP to write to memory-mapped registers (e.g. for configuration purpose). I tried to implement an AXI master IP block to write the specific registers through the GPIO slave interface on the PS. I provided target address and value to be written in the Verilog code for the IP. The write event is initiated by pressing a button on the board. Currently, when I press the button, the OS goes into a deadlock state. My questions are as follows: (1) Can I use the AXI master IP and GP
  9. Hi Jon, Yes, I also asked Xillybus about the question but it seems no one there has the experience on coresight.... I'm counting on someone in the Xilinx community may help but haven't received any reply... Anyway, thanks for your help!
  10. Hi Dan, Thank you for your information. Unfortunately, my task is to get the internal information of an ARM processor... While the IP core cannot be modified, the task is even more difficult... I will keep thinking anyway... Thanks
  11. Hi Dan, Thanks for your reply. I'm also looking for alternative option without using CoreSight to achieve my goal. I'm not sure if CoreSight is necessary in my case. Actually, the essential point in my case is that I have to implement a custom logic which can dump processor-related information (e.g. current instruction, register value, context ID, etc.) in order to track/monitor the processor state. The trace function must be triggered through pure hardware logic. For example, if I press a button on the board, my custom logic will start talking to the processor, dumping the necessary proc
  12. Hi Jon, Thanks for your reply. A quick question, is there any alternative option to achieve my objective without using CoreSight? Specifically, is there a way to dump processor-related information (e.g. current instruction, register value, etc.) without using CoreSight? Thanks.
  13. I have loaded a Xillinux OS on the Zedboard. Currently, I'm trying to enable the ARM CoreSight feature to perform program trace. My question is, is there any starter guide or tutorial for how to enable the CoreSight feature and offload the collected data to the PL? I've searched online and the only thing I can find related to CoreSight iis the official documentation, introducing the architecture, interface, etc. However, I can't find an example to start with. Any help? Thanks.
  14. Hi Dan, I think I have to start playing with the coresight and PMod and see what's going on. I appreciate all the information and help.
  15. Hi Dan, PMod is also what I've found so far from the manual. Another option might be JTAG. Both of them are available now so I think I can use any of them to extract my data. As confirmed by you, probably I would look at PMod first. My only concern is the practicality. I'm not sure with the exact number of bytes generated by my tracer before I have a solid implementation but it can be expected to be at KB or MB/s level. So which option do you think would fit my case better, PMod or JTAG? Do I need a FIFO between the connection of the PMod and my PL? Sorry if my question goes too det