Hassan Iqbal

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  1. I have followed the link @sLowe shared but it has some errors in it ( reset will never be deasserted because it relies on c3_clk0, which is never generated because the PLL is held in reset. Change line 64 of atlys_ddr_test.v to reg reset = 0; and design a proper reset controller ). Can someone please share a working reference design or a tutorial to be followed to interface Atlys Spartan 6 DDR2 using ISE. Thank you.
  2. @[email protected], Thank you for such a comprehensive answer. Since I am beginner, I have a few queries: 1. You mentioned that there is only one interface to DRAM memory. However, in Xilinx MIG, you can configure the memory to have multiple ports (screenshot attached below). Can't a 32 bit read port be used to read from the memory and a 32 bit write port be used to write to the memory at the SAME time by selecting such configuration? 2. A diagrammatic representation of your proposed solution can be: Here, I have to interface internal FIFOs (implemented in block RAM of FPGA) to MCB for reading and writing. Another solution can be to implement logic on top of DRAM (if it can be used as dual port memory?) to make it a large asynchronous FIFO itself as shown in the figure? Can the later solution be implemented to achieve the same task? If yes, then can you mention the pros and cons of the two solutions? Which solution is easier to implement etc. ? 3. Last but not the least, these solutions seem quite trivial for video processing applications in FPGA boards. Still, I am unable to find any tutorial which explains step by step procedure and gives module by module explanation of verilog code to IMPLEMENT them in any Spartan 6 development board. If there is no tutorial available, I want to understand an example (similar) code or ISE project to be able to modify it for my application. Its challenging for a beginner to implement the above solutions starting from scratch. Xilinx manuals for memory interface generator and interfacing MCBs are quite baffling for me. In this regard, can you please share some useful resource(s) which can be studied? Thank you. - Hassan
  3. Thank you @Bianca. Is there any chance that the project is available in Verilog as well? I have been learning and working on Verilog and cannot understand VHDL code of the project. Thank you again.
  4. Thank you @jpeyron. I cannot understand the retire VmodCAM projects as they are in VHDL and I have been learning and using Verilog. I have read other links already. Thanking you again and waiting for the response anxiously.
  5. Hi, For a project, I want to align two input HDMI video sources in Atlys Spartan 6. I want to implement an asynchronous FIFO which will synchronize video source B with video source A timings (picture attached). However, the FIFO should be of the size to store atleast 8 MB (frame size of each video source = 1920*1080*32 bits). How to implement this asynchronous FIFO in Atlys Spartan 6? My atlys kit has MIRA P3R1GE4JGF DDR2 IC on it instead of Micron MT47H64M16xx-25E which is in older boards of Atlys Spartan 6. I am using ISE Design Suite 14.2 and running Xapp495. The frame rate that I am working on is 120 FPS and resolution is 1080p. The pixel speed is 146.3616Mhz. If possible, then share some sample code which can be modified to implement this FIFO. Thanking you in anticipation.
  6. The link is not valid @Bianca. Please upload the 3D camera demo project. Thank you.