Thank you for such a comprehensive answer. Since I am beginner, I have a few queries:
1. You mentioned that there is only one interface to DRAM memory. However, in Xilinx MIG, you can configure the memory to have multiple ports (screenshot attached below). Can't a 32 bit read port be used to read from the memory and a 32 bit write port be used to write to the memory at the SAME time by selecting such configuration?
2. A diagrammatic representation of your proposed solution can be:
Here, I have to interface internal FIFOs (implemented in block RAM of FPGA) to MCB for reading and writing. Another solution can be to implement logic on top of DRAM (if it can be used as dual port memory?) to make it a large asynchronous FIFO itself as shown in the figure?
Can the later solution be implemented to achieve the same task? If yes, then can you mention the pros and cons of the two solutions? Which solution is easier to implement etc. ?
3. Last but not the least, these solutions seem quite trivial for video processing applications in FPGA boards. Still, I am unable to find any tutorial which explains step by step procedure and gives module by module explanation of verilog code to IMPLEMENT them in any Spartan 6 development board. If there is no tutorial available, I want to understand an example (similar) code or ISE project to be able to modify it for my application. Its challenging for a beginner to implement the above solutions starting from scratch. Xilinx manuals for memory interface generator and interfacing MCBs are quite baffling for me. In this regard, can you please share some useful resource(s) which can be studied?