hamster

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Everything posted by hamster

  1. hamster

    Arty PLL implementation?

    At the moment I never use IP blocks, and have had no trouble with the PLL primitives... here's a couple of suggestions. 1) Are you sure you have the correct package selected? I know it sounds dumb, but it happens! It should be xc7a35ticsg324-1L, but on older versions of Vivado that package isn't there. Using the Automotive -2L part seems to work.... (any suggestions from others???? 2) Try a BUFG.
  2. After finally finding a reason to start using my PMODamp3, I've created a little project that emits a very quiet 375Hz sine tone through an 8 Ohm speaker: http://hamsterworks.co.nz/mediawiki/index.php/PMODamp3 It might be of use to anybody who want to use this PMOD in a design as a starting point.
  3. As far as I can tell, that warning is always there unless you include some of the debug IP in your design. When I get issues like you have, it is normally because I've forgot to assign the clock). Can double-check the contents of your XDC file? The other problem i've had on other boards is that I've generated the bitstream for the wrong FPGA device (e.g. incorrect package) - but Vivado should pick that up for you. If you like, post the source files here we should be able to fix it pretty quickly.
  4. hamster

    PMOD connector spacing

    Also have look at https://forum.digilentinc.com/topic/1127-header-spacing-on-basys3-artix-7-fpga-board/#comment-3875 too. The spacing is the same.
  5. When I am using powered USB speakers, inserting the 3.5mm plug all the way makes the output stop. When it is not inserted all the way it makes the correct sound. Insert it all the way and it just ticks. Now that I've moved to an unpowered speaker driver, this behavior goes away. BOTHER - I've just realized the issue with my scope traces. I just looked at the schematic. The sleeve on the 3.5mm socket isn't GND, it s one side of a push-pull driver (with the tip being the other side). So I guess I need to connect both probes on the scope, (one to each speaker terminal), ground clip to the board's GND, and then use the MATH function go show A minus B to get the actual trace. You might be getting lucky as your pocket-sized DSO isn't ground-referenced.
  6. Do you have the gain jumper set at +12db? As we are sending the full range of data. I think that the maths for +12db is to multiply the samples by 4, so will clip/saturate 3/4ths of the inputs value.
  7. Hi again. The real problem (as you no doubt have worked out) is that for standalone mode without a separate MCLK signal BCLK needs to be 256x the frequency of the LRCLK. and BCLK needs to be between 2.048 MHz and 6.144 MHz (as per datasheet). This limits sample rate to 8 kHz and 24 kHz when operated in this mode. The output now sounds right, but may need to have a low impedance load on the amp for it to look right on the scope - the Class D amp makes the output look very noisy on the scope. Oh, with this code I also have to move the mclk/bclk jumper to the mclk position (as a separate mclk is being supplied) Here are my code changes and a commentary - this is just what I did. It might not be better, just different... sclk_div.v: Added a MMCM. Set up the clocking as 100 * 7 / 57 = 12.280 MHz.Generated the bclk and lrclk signal in this module, and they are the mclk clock domain (1.535MHz bit clock, 47,971 Hz sample rate - within 0.1% of 48,000Hz). oscillator.v: Put everything into the mclk clock domain, uses the transition of LRCLK to signal when to advance the waveform, rather than being clocked by directly by LRCLK i2s_tx.v: Changed to sending 32 bit frames (the high 16 bits of each channel). Moved all logic into the mclk clock domain, and it watches bclk for a transition (rather than being clocked by BCLK). LRCLK is now supplied externally to this module rather than generating within it. There now is a bug as the bit counter is no longer synced with the transitions of LRCLK - it relies on the initial conditions to be correct, which is reasonably poor form on my part! basys3_abacus_top.v: Added extra plumbing for mclk, lrclk and bclk signals. The sending out of mclk isn't really done right. It should be forwarded out with using a DDR register. Removed unused inputs and outputs - I also removed the unused constraints. `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: JUIXXXE ////////////////////////////////////////////////////////////////////////////////// module sclk_div( input clk, output wire mclk, output wire bclk, output wire lrclk ); wire clkfb; reg [13:0] mclk_count = 14'b0; MMCME2_BASE #( .BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW) .CLKFBOUT_MULT_F(7.0), // Multiply value for all CLKOUT (2.000-64.000). .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000). .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). // CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128) .CLKOUT0_DIVIDE_F(57.0), // Divide amount for CLKOUT0 (1.000-128.000). .CLKOUT1_DIVIDE(14), .CLKOUT2_DIVIDE(14), .CLKOUT3_DIVIDE(14), .CLKOUT4_DIVIDE(14), .CLKOUT5_DIVIDE(14), .CLKOUT6_DIVIDE(14), // CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99). .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT3_DUTY_CYCLE(0.5), .CLKOUT4_DUTY_CYCLE(0.5), .CLKOUT5_DUTY_CYCLE(0.5), .CLKOUT6_DUTY_CYCLE(0.5), // CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000). .CLKOUT0_PHASE(0.0), .CLKOUT1_PHASE(0.0), .CLKOUT2_PHASE(0.0), .CLKOUT3_PHASE(0.0), .CLKOUT4_PHASE(0.0), .CLKOUT5_PHASE(0.0), .CLKOUT6_PHASE(0.0), .CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE) .DIVCLK_DIVIDE(1), // Master division value (1-106) .REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999). .STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE) ) MMCME2_BASE_inst ( .CLKIN1(clk), // 1-bit input: Clock .CLKOUT0(mclk), // 1-bit output: CLKOUT0 .CLKFBOUT(clkfb), // 1-bit output: Feedback clock .CLKFBIN(clkfb), // 1-bit input: Feedback clock .PWRDWN(1'b0), // 1-bit input: Power-down .RST(1'b0) // 1-bit input: Reset ); assign bclk = mclk_count[2]; // mclk / 8 assign lrclk = mclk_count[7]; // mclk / 256 always@(posedge(mclk)) begin mclk_count = mclk_count + 1; end endmodule `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: JUIXXXE ////////////////////////////////////////////////////////////////////////////////// `define CHANNELDEPTH 32 module oscillator( input mclk, input lrclk, output reg signed [`CHANNELDEPTH-1:0] sawtooth = 0 ); reg lr_last; always@(posedge(mclk)) begin if (lr_last == 1'b0) begin if(lrclk == 1'b1) begin sawtooth = sawtooth + 10000000; end end lr_last <= lrclk; end endmodule /* * Redistribution and use in source and non-source forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in non-source form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Modified by JUIXXXE Sept. 2015 * Modified by JUIXXXE Jan. 2016 */ `define CHANNELDEPTH 32 `define logCHANNELDEPTH 5 module i2s_tx( input mclk, input bclk, input lrclk, output reg sdata = 1'b0, input signed [`CHANNELDEPTH-1:0] left_chan, input signed [`CHANNELDEPTH-1:0] right_chan ); reg lrclk_delayed = 1'b1; reg [`logCHANNELDEPTH-1:0] bit_cnt = `logCHANNELDEPTH'b0; reg signed [`CHANNELDEPTH-1:0] left; reg signed [`CHANNELDEPTH-1:0] right; reg bclk_last = 1'b0; always @(posedge mclk) begin //i2s requires the signal be delayed by one bclk cycle from the lr switch if(bclk_last == 1'b1 && bclk == 1'b0) begin if (bit_cnt == `logCHANNELDEPTH'b0) begin lrclk_delayed = ~lrclk_delayed; //read in channels at beginning of lr cycle if(lrclk_delayed) begin left = left_chan; right = right_chan; end end //assign proper chanel to sdata sdata = lrclk_delayed ? right[`CHANNELDEPTH-1 - bit_cnt] : left[`CHANNELDEPTH-1 - bit_cnt]; //increment bit count if(bit_cnt == `logCHANNELDEPTH'b01111) begin bit_cnt = `logCHANNELDEPTH'b0; end else begin bit_cnt = bit_cnt + 1; end end bclk_last = bclk; end endmodule `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: JUIXXXE ////////////////////////////////////////////////////////////////////////////////// `define CHANNELDEPTH 32 module Basys3_Abacus_Top( input clk, output reg SD_2518 = 1'b1, // Shut down - active low output wire bclk_2518, // bit clock output for 2518 output wire lrclk_2518, // lrclk aka word clock for 2518 output wire sdata_2518, // serial data output for 2518 output wire mclk_2518 // master clock for 2518 ); wire signed [`CHANNELDEPTH -1:0] sawtooth; oscillator Osc1( .mclk(mclk_2518), .lrclk(lrclk_2518), .sawtooth(sawtooth) ); i2s_tx i2stx( .bclk(bclk_2518), .lrclk(lrclk_2518), .mclk(mclk_2518), .sdata(sdata_2518), .left_chan(sawtooth), .right_chan(sawtooth) ); sclk_div sclkdiv( .clk(clk), .mclk(mclk_2518), .bclk(bclk_2518), .lrclk(lrclk_2518) ); endmodule
  8. I've got some sensible noise out of it. Will post code later on tonight.... strangly enough, the speaker output needs to be slightly unseated. But it definately is a sawtooth sounding buzz.
  9. Hi! I've got the same setup, and am getting a 1Hz ticking. How can I help you debug yours? Email me/PM me your email address, and I'll send photos...
  10. One thing I learnt today was that Vivado has a Virtual I/O IP block, that allows you to see the state of signals deep in your design. You can also use it to inject signals into your design too. I've added a little project to my Wiki which connects the switches and LEDs on the Basys3 to an instance of the Virtual I/O block. http://hamsterworks.co.nz/mediawiki/index.php/Virtual_IO (Connecting to external I/O is not really the target end-use case - it would be perfect for monitoring status signals out of transceivers and memory controllers, or observing the state of misbehaving FSMs)
  11. Your code stores an 8-bit value in an unsigned 8-bit variables (as entries in read_data) it then tests the high bit to see if the number should be negative. if so, it subtract 256 and store it back into the 8-bit variable. This results in no change. e.g. 0xFF - 0x100 equals 0xFFFFFFFF, which is -1, so far so good. when you store that back in the 8-bit unsigned number you get 0xFF (255) again. So either that code is not needed and can be removed , or it is a bug
  12. From your code u8 data_read[22]; ... readI2C(0x77, 0xAA, data_read, 22); if (data_read[0] > 127) data_read[0] = data_read[0] - 256; ... Say the first byte you read is 0xFF (255). What would you expect it to be at the end of that code?
  13. If it helps any, even without a protection resistor I/O pins a robust to shorts to ground, Vcc or a neighbouring pin. I have even measured short circuit current (50 mA is the most a pin will supply). However I live in fear of applying an overvoltage signal to a pin that isn't protected by a diode
  14. I've been playing around with a sub-$10 6-axis gyro/acceleration/attitude sensor (from http://www.dx.com/p/mpu6050-serial-6-axis-accelerometer-gyroscope-module-kalman-filtering-angle-output-for-arduino-414210 with my Basys3 (and my Raspberry Pi Zero). The sensor reports over RS232 at 115200 making it far easier to decode than with sensor that speak I2C. The short video at https://www.youtube.com/watch?v=IKylOPzRqeY shows as the senor reads from -1G (approx 0xEFFF) to +1G ( approx 0x1000) as the sensor is rotated in the Y axis. Source can be found at http://hamsterworks.co.nz/mediawiki/index.php/MPU6050_sensor_RTL
  15. The old Vivado Webpack (not the new Vivado HL Webpack, which was released in the last month or so) didn't include features like the virtual logic analyzer. The HL Webpack includes these features, so you don't really require any additional licenses. Just make sure you get the most recent version of Vivado. I think at least 2015.4 is required for the HL Webpack.
  16. hamster

    nexys 4 UART

    RS232 is pretty robust... so if it works at all it should be fine If you want to ensure the 'unknown' data is coming through without error, then maybe adding a checksum or CRC to your data to allow verification. If you want an example of reading from the serial port under Windows, take a look at http://hamsterworks.co.nz/mediawiki/index.php/Serial_Logger If you really want to validate your RS232 interface, consider adding a long period pseudo random data generator to the input of your RS232 TX module, and leave it running for a long while. However, the case that is likely to upset you is when symbols are nearly sent back-to-back (e.g. using 90% of the link bandwidth) That is where the async nature of RS232 causes grief.
  17. Everything looks great - so a silly question... are you sure you have a xc3s100e part on your board, and not the xc3s250e? (You can read the part # off the chip...) There used to be (still is?) a -250 model..
  18. What is the source you are using? Will it be trying to enforce HDCP copy protection?
  19. I just had a thought what was naggng me about the code - it's the interplay between these lines: Button <= btnD xor btnU; Direction <= btnU and not btnD; and process (Button) begin if Button='1' and Button'event then if Direction='1' then ServoPos <= ServoPos + 4; Position <= conv_std_logic_vector(ServoPos, 8); else ServoPos <= ServoPos - 4; Position <= conv_std_logic_vector(ServoPos, 8); end if; end if; end process;When a btnU is pushed, "Button" in in transition from 0 to 1 (this event is what causes the process to run). However,because "Direction" is an async function of btnU it too will be in transition from 0 to 1 too, at the same time that "Button" is. In simulation the result depends on which gets invoked first - the process or the assignment of 'Direction', and if faithfully implemented in the FPGA it will depend on the logic and routing delays on the chip - it might work some builds, and not on others. And one other tiny itch is that "Direction <= btnU and not btnD;" could just be "Direction <= btnU;", as the "and not btnD" clause doesn't change the behavior of the design, Mike
  20. Hi fpga_newbie, In addition to JColvin's comment, the part that is handling the user input is a little bit unusual. If at all possible you should avoid using the user's input as a clock signal - for plenty of reasons but most obvious is switch bounce (where the switch flickers between open and closed as the contacts move). The simplest solution for this application would be to process then button inputs once every fraction of a second (e.g at 20Hz), in much the same way as you generate the "clock_tick" signal for the PWM output. And if the switches are debounced in hardware, due to really subtle issues, these lines will not always operate consistently and might give unintended glitches. Button <= btnD xor btnU; Direction <= btnU and not btnD; The easiest (not quite bulletproof) solution is to move these lines into a clocked process, ensuring that the values of Button and Direction have been stable for long enough before they are used. Oh, and the 'position' can also overflow or underflow (e.g from 252 to 0 or from 0 to 252). However, don't let that discourage you at all - the code is looking pretty good. If you still are stuck post here again!
  21. Hi ntrstd11, For Vivado, this almost understandable Answer Record http://www.xilinx.com/support/answers/53732.html might be of help. For ISE, DATA2MEM is what you want to use (http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/data2mem.pdf) For inferred memory blocks, you sometimes need to use the floor-planning tool to work out what the BRAM instance names are. It might be a wise time to switch over to using primitives, where you can be sure that the naming will stay consistent and they won't be optimized out.
  22. hamster

    Nexus Video UART Issue

    I just had to see if this was the case - below is the code I am using to show incoming characters on the LEDs, and send '0' over and over again. Works as it should. Constraints: ## Clock set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports clk100] create_clock -period 10.000 -name clk100 -waveform {0.000 5.000} [get_ports clk100] ## LEDs set_property PACKAGE_PIN T14 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS25 [get_ports {led[0]}] set_property PACKAGE_PIN T15 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS25 [get_ports {led[1]}] set_property PACKAGE_PIN T16 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS25 [get_ports {led[2]}] set_property PACKAGE_PIN U16 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS25 [get_ports {led[3]}] set_property PACKAGE_PIN V15 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS25 [get_ports {led[4]}] set_property PACKAGE_PIN W16 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS25 [get_ports {led[5]}] set_property PACKAGE_PIN W15 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS25 [get_ports {led[6]}] set_property PACKAGE_PIN Y13 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS25 [get_ports {led[7]}] ##UART set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports uart_rx_out] set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart_tx_in] VHDL file: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity rs232_test is Port ( clk100 : in STD_LOGIC; uart_rx_out : out STD_LOGIC; uart_tx_in : in STD_LOGIC; led : out STD_LOGIC_VECTOR (7 downto 0) := (others => '0')); end rs232_test; architecture Behavioral of rs232_test is signal tx_in_counter : unsigned(19 downto 0) := (others => '0'); signal rx_out_counter : unsigned(19 downto 0) := (others => '0'); signal char_to_send : std_logic_vector(7 downto 0) := "00110000"; begin process(clk100) begin if rising_edge(clk100) then ------------------------------------------- -- Sending out the character over and over ------------------------------------------- case rx_out_counter is when to_unsigned(100000000/9600*0,20) => uart_rx_out <= '0'; when to_unsigned(100000000/9600*1,20) => uart_rx_out <= char_to_send(0); when to_unsigned(100000000/9600*2,20) => uart_rx_out <= char_to_send(1); when to_unsigned(100000000/9600*3,20) => uart_rx_out <= char_to_send(2); when to_unsigned(100000000/9600*4,20) => uart_rx_out <= char_to_send(3); when to_unsigned(100000000/9600*5,20) => uart_rx_out <= char_to_send(4); when to_unsigned(100000000/9600*6,20) => uart_rx_out <= char_to_send(5); when to_unsigned(100000000/9600*7,20) => uart_rx_out <= char_to_send(6); when to_unsigned(100000000/9600*8,20) => uart_rx_out <= char_to_send(7); when to_unsigned(100000000/9600*9,20) => uart_rx_out <= '1'; when others => NULL; end case; rx_out_counter <= rx_out_counter + 1; ---------------------------------------------- -- Receiving the character and show it on LEDs ---------------------------------------------- if tx_in_counter = 0 then if uart_tx_in = '0' then tx_in_counter <= tx_in_counter + 1; end if; else tx_in_counter <= tx_in_counter + 1; case tx_in_counter is when to_unsigned(100000000/9600*15/10,20) => led(0) <= uart_tx_in; when to_unsigned(100000000/9600*25/10,20) => led(1) <= uart_tx_in; when to_unsigned(100000000/9600*35/10,20) => led(2) <= uart_tx_in; when to_unsigned(100000000/9600*45/10,20) => led(3) <= uart_tx_in; when to_unsigned(100000000/9600*55/10,20) => led(4) <= uart_tx_in; when to_unsigned(100000000/9600*65/10,20) => led(5) <= uart_tx_in; when to_unsigned(100000000/9600*75/10,20) => led(6) <= uart_tx_in; when to_unsigned(100000000/9600*85/10,20) => led(7) <= uart_tx_in; when to_unsigned(100000000/9600*95/10,20) => tx_in_counter <= (others => '0'); when others => end case; end if; end if; end process; end Behavioral;
  23. Here's what I wrote for use on a Raspberry Pi - Hope it helps! /************************************************* * Pressure setup BMP085 * *************************************************/ static int pressure_setup(int fd) { char data[22]; /* Set address of the device we wish to speak to */ if (ioctl(fd, I2C_SLAVE, p_address) < 0) { printf("Unable to get bus access to talk to pressure sensor\n"); return -1; } i2c_seek(fd, 0xAA); if (read(fd, data, 22) != 22){ printf("Unable to read calibrationd data from presure sensor\n"); return -1; } p_calib.ac1 = (data[ 0]<<8) | data[ 1]; p_calib.ac2 = (data[ 2]<<8) | data[ 3]; p_calib.ac3 = (data[ 4]<<8) | data[ 5]; p_calib.ac4 = (data[ 6]<<8) | data[ 7]; p_calib.ac5 = (data[ 8]<<8) | data[ 9]; p_calib.ac6 = (data[10]<<8) | data[11]; p_calib.b1 = (data[12]<<8) | data[13]; p_calib.b2 = (data[14]<<8) | data[15]; p_calib.mb = (data[16]<<8) | data[17]; p_calib.mc = (data[18]<<8) | data[19]; p_calib.md = (data[20]<<8) | data[21]; return 0; } /************************************************ * Pressure read BMP085 * *************************************************/ static int read_pressure(int fd) { unsigned char oss = 3; unsigned char buf[3]; /* chech the size of all of these! */ long ut,up; long x1,x2,x3; long b3,b5,b6; unsigned long b4,b7; long t,p; float alt; /* Set address of the device we wish to speak to */ if (ioctl(fd, I2C_SLAVE, p_address) < 0) { printf("Unable to get bus access to pressure sensor\n"); return -1; } /* Start conversion to get temperature */ if(i2c_write_reg(fd, 0xF4, 0x2E) < 0) return -1; usleep(4500); i2c_seek(fd, 0xF6); if (read(fd, buf, 2) != 2){ printf("Unable to read from pressure sensor\n"); return -1; } ut = (buf[0] <<8) | buf[1]; if(i2c_write_reg(fd, 0xF4, 0x34 + (oss <<6)) < 0) return -1; usleep(25500); /* Changes depending on value of oss */ i2c_seek(fd, 0xF6); if (read(fd, buf, 3) != 3){ printf("Unable to read from pressure sensor\n"); return -1; } /* Display the register values */ up = ((buf[0] <<16) | (buf[1]<<8) | buf[2]) >> (8-oss); /* Calculate the true temp */ x1 = (ut - p_calib.ac6) * p_calib.ac5 / (1<<15); x2 = (p_calib.mc *(1<<11)) / (x1 + p_calib.md); b5 = x1+x2; t = (b5+8)/(1<<4); /* Calc pressure */ b6 = b5 - 4000; x1 = (p_calib.b2*((b6*b6)>>12))>>11; x2 = (p_calib.ac2*b6)>>11; x3 = x1+x2; b3 = (((p_calib.ac1*4+x3)<<oss)+2)/4; x1 = (p_calib.ac3*b6)>>13; x2 = (p_calib.b1*(b6*b6)>>12)>>16; x3 = ((x1+x2)+2)>>2; b4 = (p_calib.ac4*((unsigned long)x3+32768))>>15; b7 = ((unsigned long)up-b3)*(50000>>oss); if(b7 < 0x80000000) p = (b7*2)/b4; else p = (b7/b4)*2; x1 = (p>>8)*(p>>8); x1 = (x1*3038)>>16; x2 = (-7357*p)>>16; p = p + ((x1+x2+3781)>>4); alt = 44330.0 * (1-pow(p/101325.0,1.0/5.255)); printf("T = %li.%li C, P = %li Pa alt = %7.2f m", t/10, t%10, p, alt); return 0; }
  24. Can you answer this two questions.... 1. If the vsync pin is always an output pin (and never used as input), what will using a pull-up or pull-down resistor on that pin achieve? 2. What UCF entries do you have for the vsync pin?
  25. I installed the Vivado 15.4 HLx Webpack edition, and grabbed the latest HLx license. it does now include the virtual Logic Analyzer - I tested it on my Basys3 this morning.