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Everything posted by hamster

  1. Hi! It looks like you problem is that you are using the "non-clock" pin (the button) as a clocking signal. This confuses the tools. You have a few options. 1. Use an actual, stable,clock and then increase the count when your design sees the rising edge on the signal if rising_edge(clk) then if sw_in = '1' and sw_last = '0' then ... increment the count here ... end if; sw_last = sw_in; end if; 2. send the signal through a clock buffer, forcing it onto the clocking networks. library UNISIM; use UNISIM.VComponents.all; ..... clk_buffer: BUFG PORT MAP ( I => sw_in, O => sw_buffered); (just remember to use the then you can use if rising_edge(swtich_buffered) then ... increment the count here ... end if; 3. You can add constraints or implementation options to allow you to ignore the errors. However these solutions have issues due to switch bounce, and/or the need to correctly synchronize the input signal to the local clock domain. Option 1 is the best pattern to follow to eventually end up with a working design.
  2. Oh, XAPP585 ( https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf ) hints at this design.
  3. Somebody recently told me something that others might find helpful. When you use ISERDES in master/slave configuration to receive bits, you don't have a phase detector, or any other way to work out if you are sampling at the optimal time. However, if you don't use a master/slave configuration, you can use two ISERDES blocks to sample the same incoming signals - each with their own separately adjustable IDELAY block. You can then adjust the input delay to identify where the transitions signal are. The downside is that you can't process larger symbols - if you want to process 10-bit symbols you need to make a 'gear box' to accept ten 8-bit works, and emits eigth 10-bit words to the rest of the design. I might give this a test on my HDMI design when I get some free time...
  4. I'm late to the party, but... ...given that the Nexys Video can transmit at 435 MB/s (for 1080p video) using the standard SERDES pins, 4MB should take about 9.6ms - this is using three data pairs plus a clock pair. Sending the clock to the sink would be the way to go, as it avoids the need for clock recovery, (where you really need to use the transceivers) However, PMOD connectors are not very good for very high frequency signals - I once managed to get 500Mb/s through 0.1" connector and 200mm jumper wires, but it wasn't really a properly engineered solution. You would be very, really lucky to get 50MB/s through each pair.
  5. hamster

    Luigi Sabatini

    Hi! I have a Genesys2, and have never needed to use Adept. I design in Vivado and use the Vivado suit to program the FPGA (the JTAG interface has native support), The J15 USB<->UART bridge uses the standard FTDI drivers to implement the virtual serial port.
  6. Hi! The top-level signal spi_ss_io has not been given a because it has already been taken by something else. Something to do with "shield_dp0_dp19" at a guess. Mike
  7. Have you ever thought about adding PMOD which has I2S input? Or maybe input and output using something like http://www.nxp.com/products/media-and-audio-processing/data-converters/audio-converters/audio-codec/ultra-low-power-audio-codec:SGTL5000
  8. Hi Megaxoplasma, To control the LED intensity you only switch it on part of the time, using a technique called Pulse Width Modulation (a.k.a. PWM) If you switch the LED on and off quick enough, you are only able to see the average intensity. To avoid flicker you need to switch it at least on and off at least 50 times per second.
  9. hamster

    Nexys Video

    Hi! I've worked with the DisplayPort output on the Nexys Video. . The Nexys Video only has a mini DisplayPort Output so can't be used to receive data. It really is configured only for sending data at 2.70Gb/s (20x the reference clock of 135 MHz) The page 47 of the transceiver user guide (https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf) indicates that: PLLfreq = Refclock * N1 * N2 / M, ...and that the PLL frequency must be between 1.6 and 3.3 GHz. The line rate is: LineRate = PLLFreq 2 * / D. With N1 = 5, N2 = 5, M=2 the PLL Freq will be 1687.5 MHz, and with a D of 1, the data rate will be 3375, which is just out of spec, but might just work Hey! Wow! I've just seen how you can run the DisplayPort interface at 1.62 Gb/s, reference clock of 135, with N1 of 3, N2 of 4 gives a PLL frequency of 1620 GHz, so with a D value of 2, you get 1.62Gb/s.... sweet!
  10. hamster

    ISE for Arty board

    Sadly the documentation is accurate - only a selected few 7-series devices are supported in ISE - see https://www.xilinx.com/publications/matrix/Software_matrix.pdf If you really want to make a rod for your own back, nothing stops you from using ISE to generate HDL files that you then include in a Vivado project... Vivado does have a block diagram mode, that is sort of schematic capture, allowing you to connect IP blocks together, maybe that will meet your needs?
  11. Yes, you need to set CLOCK_DEDICATED_ROUTE = FALSE in your constraints file, which allows the tools to run clock signals over the connections that usually transfer data signals.
  12. Hi! I don't have ISE installed at the moment but have looked at the code.... I see you have the clocks buffered with BUFG - great stuff! The most likely problem is this: JA1 <= ClkOut80; JA2 <= ClkOut80P180; It trys to take the signals from the clocking network and send them through the data output, which are designed to generic take data signals from the FPGA fabric. There is an easy solution to this - use a DDR output buffer to output a '0' through the first half of the cycle and a '1' through the second half (or the other way around for the P180 signal): JA1_out_ddr: ODDR2 generic map(DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC") port map (C0 => ClkOut80, C1 => ClkOut80P180, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1', Q => JA1); JA2_out_ddr: ODDR2 generic map(DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC") port map (C0 => ClkOut80P180, C1 => ClkOut80, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1', Q => JA2); or if you want to avoid using the P180 clock (to save resources): JA1_out_ddr: ODDR2 generic map(DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC") port map (C0 => ClkOut80, C1 => not ClkOut80, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1', Q => JA1); JA2_out_ddr: ODDR2 generic map(DDR_ALIGNMENT => "C0", INIT => '0', SRTYPE => "ASYNC") port map (C0 => not ClkOut80, C1 => ClkOut80, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1', Q => JA2); (Or you can swap D0 => '1', D1 => '0' for the second DDR, keeping C0 => ClkOut80, C1 => not ClkOut80) Like I said, I don't have ISE in so can't test at the moment, so this might have some silly errors in it You can avoid the "COMPONENT" declarations for primitives by using the library, which can avoid some errors... library UNISIM; use UNISIM.VComponents.all;
  13. As the high speed Transceivers are not available on the Arty, your maximum per-pin bandwidth is about 1Gb/s, which will be too slow for a high speed JESD204B interface.
  14. Hi FlyingBlindOnARocketCycle, You design might be the wrong way for an efficient hardware implementation, but fixed point is definitely the best way. That way, if you are using a 100MHz clock, the math will be something like: reset_count = (100000000/n)-1; Integer division can be converted directly to hardware. An efficient hardware implementation (from a hardware resources point of view) might be a pre-calculated lookup table. If you include the 24 bits for the reset count, and 21 bits for the seven segment patterns. A 256 x 45-bit lookup table will fit in one block RAM, and will pretty much remove the need for any complex logic. Oh, and make sure that your counter counts down, rather than up. if counter = 0 then counter <= reset_count_table(to_integer(unsigned(freqency_index))); -- then do the stuff you want to do every so many cycles. else counter <= counter-1; end if; If you count up, it is very easy for errors to creep in, giving runt pulses, long gaps or other odd behavior.
  15. hamster

    Arty: Output Frequency

    The high speed PMODs can go very fast, but you have to work the way high speed signals work, taking great care. That may mean differential signalling, correct termination and careful PCB layout. I have been able to get 500Mb/s to work, but that also included a good bit of luck. With single ended signalling you will have very poor results.
  16. Hi! From the data sheet,OSERDES supports LVDS data rates at up to 1250Gb/s (grades -2 & -3). (Table 15 of http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf). However, I can confirm that at least my board Nexys Video works fine at 1.475 Gb/s, with a few timing warnings on the IO clocking networks.
  17. I have had the same behaviour on a very full design. I put it down to drawing too much power from the power supplies causing the FPGA to reset. Not sure if this is 100% what is going on, but a smaller design worked fine.
  18. hamster

    PLL Clocks on Arty

    Oh, and to go along with Dan's answer... The more recent versions of Vivado seem to have become much more picky about the use of clock buffers, throwing errors if you don't include them. Here's one example of using global clock buffers: library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; entity clocking is Port ( clk100MHz : in STD_LOGIC; clk125MHz : out STD_LOGIC; clk125MHz90 : out STD_LOGIC); end clocking; architecture Behavioral of clocking is signal clk100MHz_buffered : std_logic := '0'; signal clkfb : std_logic := '0'; signal clk125MHz_unbuffered : STD_LOGIC; signal clk125MHz90_unbuffered : STD_LOGIC; begin bufg_100: BUFG port map ( i => clk100MHz, o => clk100MHz_buffered ); ------------------------------------------------------- -- Generate a 125MHz clock from the 100MHz -- system clock ------------------------------------------------------- pll_clocking : PLLE2_BASE generic map ( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT => 10, CLKFBOUT_PHASE => 0.0, CLKIN1_PERIOD => 10.0, -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128) CLKOUT0_DIVIDE => 8, CLKOUT1_DIVIDE => 20, CLKOUT2_DIVIDE => 40, CLKOUT3_DIVIDE => 8, CLKOUT4_DIVIDE => 16, CLKOUT5_DIVIDE => 16, -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999). CLKOUT0_DUTY_CYCLE => 0.5, CLKOUT1_DUTY_CYCLE => 0.5, CLKOUT2_DUTY_CYCLE => 0.5, CLKOUT3_DUTY_CYCLE => 0.5, CLKOUT4_DUTY_CYCLE => 0.5, CLKOUT5_DUTY_CYCLE => 0.5, -- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000). CLKOUT0_PHASE => 0.0, CLKOUT1_PHASE => 0.0, CLKOUT2_PHASE => 0.0, CLKOUT3_PHASE => -270.0, CLKOUT4_PHASE => 0.0, CLKOUT5_PHASE => 0.0, DIVCLK_DIVIDE => 1, REF_JITTER1 => 0.0, STARTUP_WAIT => "FALSE" ) port map ( CLKIN1 => CLK100MHz_buffered, CLKOUT0 => CLK125MHz_unbuffered, CLKOUT1 => open, CLKOUT2 => open, CLKOUT3 => CLK125MHz90_unbuffered, CLKOUT4 => open, CLKOUT5 => open, LOCKED => open, PWRDWN => '0', RST => '0', CLKFBOUT => clkfb, CLKFBIN => clkfb ); bufg_125Mhz: BUFG port map ( i => clk125MHz_unbuffered, o => clk125MHz ); bufg_125Mhz90: BUFG port map ( i => clk125MHz90_unbuffered, o => clk125MHz90 ); end Behavioral;
  19. It is called 'CPU affinity' - Google that and you should get an answer (or use 'man taskset' IIRC)
  20. If you were to use the Xilinx licensed HDMI IP block this would be possible, and there are a few projects out on the web that include sound in their non-IP based HDMI implementation (e.g. https://github.com/charcole/NeoGeoHDMI)
  21. Hi, In the HDMI specs the minimum resolution of 640x480 @ 60Hz, which has a pixel clock frequency is of about 25MHz (25.175 MHz IIRC) - see http://www.microprocessor.org/HDMISpecification13a.pdf If your pixel clock is lower than this you will have to add a scan-line doubler, and send each pixel twice (to make each pixel into a 2x2 square).
  22. I've been beavering away on a large project, but ended up thinking about how small a Serial TX module could be. While out splitting firewood stumbled over the idea that takes it down top 12 LUTs and 11 flip-flops library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity tiny_rs232_tx is Port ( clk : in STD_LOGIC; bit_tick : in STD_LOGIC; data : in STD_LOGIC_VECTOR(7 downto 0); data_enable : in STD_LOGIC; tx : out STD_LOGIC := '1'; busy : out STD_LOGIC ); end tiny_rs232_tx; architecture Behavioral of tiny_rs232_tx is signal shift_reg : std_logic_vector(9 downto 0) := (others => '1'); signal i_busy : std_logic; begin busy <= i_busy; with shift_reg select i_busy <= '0' when "0000000000", '1' when others; clk_proc: process(clk) begin if rising_edge(clk) then if i_busy = '0' and data_enable = '1' then shift_reg <= '1' & data & '0'; end if; if bit_tick = '1' then if i_busy = '1' then tx <= shift_reg(0); shift_reg <= '0' & shift_reg(9 downto 1); end if; end if; end if; end process; end Behavioral;
  23. hamster

    Connect HDMI to ZedBoard

    Hi Rohit, That project was indeed done in ISE (as it supports Zynq). If you send me a few personal messages (or email) I could most likely help you out. Mike
  24. Oh, one thing to be careful of is that I2S samples are signed, so don't test with alternating between 0x0000 and 0xFFFF (0 and -1) as it will be very quiet, 0xC000 and 0x4000 are a better option for first tests. These values do however these values make perfect test values for verifying the alignment of the data vs the LR clock And why we are on the subject, I2S comes with a few different options for the alignment of the first bit of the same to the edge of the LR clock, and the justification of the samples within the frame (e.g. does the padding proceed or follow the sample values). I've got something that generates a valid I2S stream here: http://hamsterworks.co.nz/mediawiki/index.php/PMODamp3 - you might want to simulate it and see if it matches your implementation.
  25. I tried really hard to avoid coding it for you, but here is code that has the spirit of what you need to do. I haven't tried to compile or debug it, but it should provide a framework that will guide you.... ... the headers and top of the module.... SIGNAL COUNT : INTEGER:=0; SIGNAL I : integer range 0 to 2000; BEGIN -------------------------------------------------------------------------------------- -- I am pretty sure that this will divide the clock by four -------------------------------------------------------------------------------------- PROCESS(CLK, RESET) BEGIN IF RESET='1' THEN COUNT<=0; TEMP<='0'; ELSIF RISING_EDGE(CLOCK_50) THEN COUNT<=COUNT+1; IF COUNT=1 THEN TEMP<=NOT TEMP; COUNT<=0; END IF; END IF; CLK_OUT<=TEMP; END PROCESS; PROCESS(CLK,RESET) BEGIN IF RESET='1' THEN I <=0; ELSIF RISING_EDGE(CLOCK_50) THEN IF I < 5 THEN IF(KEY(0)='1' AND TX_BUSY='0') THEN TX_DATA<=SW(7 DOWNTO 0); TX_START<='1'; I <= I+1; ELSE TX_START<='0'; END IF; END IF; END IF; END PROCESS; ... the rest of the code....