hamster

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Everything posted by hamster

  1. hamster

    Basys �

    (Argh! Why when I post does the edit window remain open with txt in it, so I click "Save Changes" again and double-post???)
  2. hamster

    Basys �

    One other option if you need to drive high power motors, is to use a RC plane speed controller to drive the motor. Something like http://www.dx.com/p/flying-30a-bec-electronic-speed-controller-for-brushless-motors-esc-11981 costs under $12 and will drive up to 360W. If you need to drive in reverse as well, then get a RC car speed controller, some models can also drive brushed (standard DC) motors. That then reduces the FPGA engineering to generating a 50Hz signal with duty cycle of between 5% and 10% (i.e. a pulse between 1ms and 2ms, every 20ms) - have a look at http://www.fpga4fun.com/RCServos.html If you really want to avoid soldering, then using http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-CON3 would allow you to connect up to four motors. As a bonus it also gives the option for extra isolation between the FPGA and motors - if you are building your own PCB you could even put an opto-coupler in the signal path, which could completely electrically isolate the FPGA from the (noisy) motor and battery. Mike
  3. hamster

    Basys �

    Hi, You really haven't provided enough information for anybody to give you a sensible answer - what sort of motor? Do you need speed control? Forward and reverse?.... Mike
  4. It depends how you do it... If you do it like this you will be safe: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL; entity gated_clock_test is Port ( clk : in STD_LOGIC; control_sw : in STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is signal counter : unsigned(7 downto 0); begin leds <= std_logic_vector(counter); p: process(clk) begin if rising_edge(clk) and control_sw = '1' then counter <= counter+1; end if; end process; end Behavioral; If you do it like this you will get a gated clock warning: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL; entity gated_clock_test is Port ( clk : in STD_LOGIC; control_sw : in STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is signal counter : unsigned(7 downto 0); signal gated_clock : std_logic;begin leds <= std_logic_vector(counter); gated_clock <= clk and control_sw; p: process(gated_clock) begin if rising_edge(gated_clock) then counter <= counter+1; end if; end process; end Behavioral;You can however do exactly the same like this, using a clock buffer with a 'clock enable' signal: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;Library UNISIM;use UNISIM.vcomponents.all; entity gated_clock_test is Port ( clk : in STD_LOGIC; control_sw : in STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is signal counter : unsigned(7 downto 0); signal gated_clock : std_logic;begin leds <= std_logic_vector(counter); BUFGCE_inst : BUFGCE port map ( O => gated_clock, -- Clock buffer ouptput CE => control_sw, -- Clock enable input I => clk -- Clock buffer input ); p: process(gated_clock) begin if rising_edge(gated_clock) then counter <= counter+1; end if; end process; end Behavioral;But if you really just need relatively slow logic then a clock divider is the way to go - everything stays in the same clock domain, so you don't get timing issues when slow logic talks to fast logic: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;Library UNISIM;use UNISIM.vcomponents.all; entity gated_clock_test is Port ( clk : in STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is signal counter : unsigned(7 downto 0); signal two_in_nine : std_logic_vector(8 downto 0) := "100010000"; signal control_2_in_9 : std_logic := '0';begin leds <= std_logic_vector(counter); ----------------------------------------- -- Process to manage the the clock enable -----------------------------------------divide_clock: process(clk) begin if rising_edge(clk) then control_2_in_9 <= two_in_nine(0); two_in_nine <= two_in_nine(7 downto 0) & two_in_nine(8); end if; end process; -------------------------------- -- Process to do the actual work --------------------------------p: process(clk) begin if rising_edge(clk) and control_2_in_9 = '1' then counter <= counter+1; end if; end process; end Behavioral;
  5. hamster

    DVI Receive on Zybo

    Actually I had a look at the schematics can somebody explain how it works as a dual-mode (source or sink) interface? From the '7-series FPGA SelectIO resources' - "The TMDS standard requires external 50Ω pull-up resistors to 3.3V on the inputs. TMDS inputs do not require differential input termination resistors." I read this to be the same as with the Spartan-6 series (and other CML) where the source should not have any termination resistors. (Picture snipped from the "Spartan-6 SelectIO Resources" pdf) Won't the termination be wrong if the port is used as an source, as it will be terminated twice, once at the source and once at the sink?
  6. hamster

    DVI Receive on Zybo

    I've been doing a bit of playing around with DVI-D lately (see http://hamsterworks.co.nz/mediawiki/index.php/HDMI_Input) on Spartan 6, so if you are desperate to get started maybe it will help. The source project should easily port through to Vivado, but I haven't started looking at the 7-series SERDES to see how hard it will be to tweak the "input_serailizer.vhd" and the required clocking. It might just work :-)
  7. Plenty of ways...but your question is a bit vague. Here are a few options. - You can supply an logic-level clock to one the PMOD pins, and use that as the clock signal in your design. - You can use the on-board clock and make a fractional clock generator (which will have pretty bad jitter, as the resolution is limited by the clock rate of the fractional clock generator) - You can use a "clock enable" signal that is not asserted on every clock cycle, to slow your design down - You can use a Digital Clock Manager (DCM) to generate quite a few different clocks, and then switch between them (perfect if all the clock rates are known in advance) - You can use a DCM_CLKGEN, where you can reprogram the DCM's multiply or divide frequency on the fly (e.g. to switch a large amount of logic between a few fixed clocks) .... Or you can do a mix of the above techniques! It really depends on WHY you want a variable clock, and HOW you intend to use it... what are you trying to do?
  8. Last night I was wondering if you could use the analog VGA port on my Basys3 to generate useful high frequency (3MHz - 30 MHz) signals. Well it turns out you can, as long as you are not too fussy about noise, which is at about -32 db. See http://hamsterworks.co.nz/mediawiki/index.php/DDS_via_a_VGA_port for details
  9. My name is Mike, and I've developed a bit of an obsession with FPGAs. You might be able to find some project ideas or inspiration on my WIki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_Projects I'm always happy to talk FPGAs, so feel free to drop me an email sometime
  10. Hi LariSan, I've had my Basys3 for about a week, and I like it lots - it is a much, much bigger faster FPGA than the Basys2. Is there any reason why the DVD-style cases were discontinued? I quite like being able to keep a board in my laptop bag, and I imagine that EE or CS students found this a great feature.
  11. I've just finished porting the Bombjack FPGA implementation from a Spartan 6 board to my Basys3 board. As it was my first attempt at anything meaningful with Vivado the code base is a bit messy, but if anybody wants a copy just drop me a message. The only changes required were to replace the DCM_CLOCKGEN with a MMCM, and to look into some weird timing problems as old arcade games did not us a fully synchronous design. However please note - I can give you the hardware design files, but I am unable to redistribute the actual ROM images that are required to implement the game.
  12. hamster

    PMOD as GPIO

    Hi Alvin, Have you added a constraint to bind the signal to the physical pin? Just giving it the same name as the pin isn't enough... The master constraint file for the Nexys4 can be grabbed from http://www.digilentinc.com/Data/Products/NEXYS4/Nexys4_Master_xdc.zip, and then you will need to add the lines like this to your projects Implementation Constraint file. NET "JC0" LOC = "K2" | IOSTANDARD = "LVCMOS33"; This will cause the signal JC0 to be connected on the "K2" pin on the FPGA package, Mike
  13. hamster

    Oscilloscope for Nexys 4

    Hi JC2694, The short answer is you want to get the best scope that your budget allows. But for a more complete answer, the document you want is http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf - in particular table 15. "DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) is between 960Mb/s and 1250Mb/s, depending on speed grade." However, you are very unlikely to use these speeds (or be able to afford a Oscope that can work at them). There are tools like Xilinx's ChipScope that allow you to see what the signals look like on the inside of the the FPGA.