hamster

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Everything posted by hamster

  1. hamster

    Basys �

    Actually, there is demo project on the PMOD web page... http://www.digilentinc.com/Data/Products/PMB/PModHB3_Demo.zip
  2. hamster

    Basys �

    Hi, Assuming you have wired up everything correctly, and you want to use four push buttons to drive a motor at one of four speeds (backwards fuil power, backwards half power, forwards half power, forwards full power) In sort of VHDL psuedo-code you want to do do something like this. I haven't read the PMOD's reference manual, so I might have the logic level the wrong way around (active low vs active high for the PMOD's enable signal). ... signal counter : unsigned (17 downto 0) := 0; signal pwn_50_percent : std_logic := '0'; ... process(clk) begin if rising_edge(clk) then case buttons is when "1000" => -- Backwards full speed pmod_dir = '1'; pmod_enable = '1'; when "0100" => - Backwards half speed pmod_dir = '1'; pmod_enable = pwn_50_percent; when "0010" => - Forward half speed pmod_dir = '0'; pmod_enable = pwn_50_percent; when "0001" => - Forward half speed pmod_dir = '0'; pmod_enable = pwn_50_percent; when others => -- no buttons, or multiple buttons so do nothing pmod_dir = '0'; pmod_enable = '0'; end case; -- Using a counter to make a 50% PWM signal counter <= counter + 1; pwn_50_percent = counter(17); -- PWM Freq = clk / (256*1024), 50% duty cycle. end if;; end process;
  3. It's not on an Atlys, but here is how to make a DDR frame buffer on anther Spartan 6 board, using the on-chip Memory Controller: http://hamsterworks.co.nz/mediawiki/index.php?title=MCB_Frame_Buffer You will also want to have a good read of Spartan-6 FPGA Memory Controller User Guide (http://www.xilinx.com/support/documentation/user_guides/ug388.pdf) to start making sense of it all.
  4. This post might be of use to you: http://www.gadgetfactory.net/2013/09/having-problems-installing-xilinx-ise-on-windows-8-64bit-here-is-a-fix-video-included/
  5. I don't have a PMODmaxsonar, but reading the reference manual is seems that you only need to connect pins 4, 5 and 6 to the BASYS2 (PWM output, GND and Vcc). You can connect the other pins but it does not seem to be essential. You should be careful with pin 1, as it is an analogue output - I suggest you configure the relevant FPGA pin as an input to prevent excessive power usage So they should be configured as follows (assuming you are using PMOD JA): JA1 - Input - ignored, it is the Analogue output JA2 - Input with pull-up, or an output set to '1', to enable the sonar module. JA3 - Input - Ignored - it is the serial data stream from the PMODsonar JA4 - Input - the PWM distance signal. GND - Ground Vcc - 3.3V Distance can then be obtained by counting the length of the PWM input pulse. if rising_edge(clk) then if JA4_sampled = '1' then counter <= counter + 1; elsif counter > 0 then pulse_length <= counter; counter <= (others => '0'); end if; -- Sample the PWM signal into a register, to avoid problems with an async signal. JA4_sampled <= JA4; end if; You can actually avoid a lot of math required to convert a 'count' into a distance. In the manual it says that the pulse with is 147µs per inch, and if your FGA design is running at 100MHz you can do this: if rising_edge(clk) then if JA4_sampled = '1' then if counter = 14699 then -- every 147us add an inch to the distance to the target inches <= inches + 1; counter <= (others => '0'); else counter <= counter + 1; end if; elsif counter > 0 or inches > 0 then -- set the output then reset the counters range <= inches; counter <= (others => '0'); range <= (others => '0'); end if; -- Sample the PWM signal into a register, to avoid problems with an async signal. JA4_sampled <= JA4; end if; And then your "range" output is the range in inches, without needing to use any complex math
  6. I was having a look at Learn@Digilent, and noticed that "Resistance and Ohm's Law" shows up in the Digital/FPGA topic, not under the Analog topic. I like the "Design Challenges", I would love to see a few more of them! A follow-on from the stopwatch could be a full digital clock (e.g. display hours and minutes). Some advanced design challenges to explore doing things wrong would be interesting too - e.g. Problems with switch bounce Switch bounce as the mechanics within a switch or push-button make intermittent connection as the move from 'open' to 'closed'. Build a design that counts how many times a switch 'bounces'. You can either display it on the 7 segment display or even just a binary count on the LEDs. Do some switches have more bounce than others? Would you expect the amount of bounce to change as the switch ages? Make a design that counts how long a switch or button bounces for. Now extend your design to include logic to "debounce" the switch, and prove that this now works correctly, with only a single transition being registered for each switch "open/close" Problems with async resets A reset signal should be synchronised with the local clock before being acted upon, otherwise different parts of a design can come out of reset during different clock cycles. This design challenge is different than most - you need to make a design that fails to reset correctly when a push-button is released, even though it is correctly coded. HInt: Look at this code. if rising edge(clk) then if reset = '1' then toggle <= switches; else toggle <= not toggle. end if; end if; If switches are set to all "0"s or all "1"s then "toggle" should never have anything but all 1s or all 0s - anything else is an error. Important make sure you use external inputs to prevent the optimizer from collapsing your logic through constant propagation. Can you make a reset that works reliably? Problems with Metastability When you have asynchronous signals it is possible for flip-flops to get stuck in an "undecided" state for a short duration causing system errors. Are you able to make a design that successfully proves that this can occur, and provide a rough estimate of how often it occurs in your design The Spartan 6 FPGA has a start-up clock that can be used in your design to provide a second independent clock signal.
  7. hamster

    Basys �

    (Argh! Why when I post does the edit window remain open with txt in it, so I click "Save Changes" again and double-post???)
  8. hamster

    Basys �

    One other option if you need to drive high power motors, is to use a RC plane speed controller to drive the motor. Something like http://www.dx.com/p/flying-30a-bec-electronic-speed-controller-for-brushless-motors-esc-11981 costs under $12 and will drive up to 360W. If you need to drive in reverse as well, then get a RC car speed controller, some models can also drive brushed (standard DC) motors. That then reduces the FPGA engineering to generating a 50Hz signal with duty cycle of between 5% and 10% (i.e. a pulse between 1ms and 2ms, every 20ms) - have a look at http://www.fpga4fun.com/RCServos.html If you really want to avoid soldering, then using http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-CON3 would allow you to connect up to four motors. As a bonus it also gives the option for extra isolation between the FPGA and motors - if you are building your own PCB you could even put an opto-coupler in the signal path, which could completely electrically isolate the FPGA from the (noisy) motor and battery. Mike
  9. hamster

    Basys �

    Hi, You really haven't provided enough information for anybody to give you a sensible answer - what sort of motor? Do you need speed control? Forward and reverse?.... Mike
  10. It depends how you do it... If you do it like this you will be safe: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL; entity gated_clock_test is Port ( clk : in STD_LOGIC; control_sw : in STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is signal counter : unsigned(7 downto 0); begin leds <= std_logic_vector(counter); p: process(clk) begin if rising_edge(clk) and control_sw = '1' then counter <= counter+1; end if; end process; end Behavioral; If you do it like this you will get a gated clock warning: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL; entity gated_clock_test is Port ( clk : in STD_LOGIC; control_sw : in STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is signal counter : unsigned(7 downto 0); signal gated_clock : std_logic;begin leds <= std_logic_vector(counter); gated_clock <= clk and control_sw; p: process(gated_clock) begin if rising_edge(gated_clock) then counter <= counter+1; end if; end process; end Behavioral;You can however do exactly the same like this, using a clock buffer with a 'clock enable' signal: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;Library UNISIM;use UNISIM.vcomponents.all; entity gated_clock_test is Port ( clk : in STD_LOGIC; control_sw : in STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is signal counter : unsigned(7 downto 0); signal gated_clock : std_logic;begin leds <= std_logic_vector(counter); BUFGCE_inst : BUFGCE port map ( O => gated_clock, -- Clock buffer ouptput CE => control_sw, -- Clock enable input I => clk -- Clock buffer input ); p: process(gated_clock) begin if rising_edge(gated_clock) then counter <= counter+1; end if; end process; end Behavioral;But if you really just need relatively slow logic then a clock divider is the way to go - everything stays in the same clock domain, so you don't get timing issues when slow logic talks to fast logic: library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;Library UNISIM;use UNISIM.vcomponents.all; entity gated_clock_test is Port ( clk : in STD_LOGIC; leds : out STD_LOGIC_VECTOR (7 downto 0));end gated_clock_test; architecture Behavioral of gated_clock_test is signal counter : unsigned(7 downto 0); signal two_in_nine : std_logic_vector(8 downto 0) := "100010000"; signal control_2_in_9 : std_logic := '0';begin leds <= std_logic_vector(counter); ----------------------------------------- -- Process to manage the the clock enable -----------------------------------------divide_clock: process(clk) begin if rising_edge(clk) then control_2_in_9 <= two_in_nine(0); two_in_nine <= two_in_nine(7 downto 0) & two_in_nine(8); end if; end process; -------------------------------- -- Process to do the actual work --------------------------------p: process(clk) begin if rising_edge(clk) and control_2_in_9 = '1' then counter <= counter+1; end if; end process; end Behavioral;
  11. hamster

    DVI Receive on Zybo

    Actually I had a look at the schematics can somebody explain how it works as a dual-mode (source or sink) interface? From the '7-series FPGA SelectIO resources' - "The TMDS standard requires external 50Ω pull-up resistors to 3.3V on the inputs. TMDS inputs do not require differential input termination resistors." I read this to be the same as with the Spartan-6 series (and other CML) where the source should not have any termination resistors. (Picture snipped from the "Spartan-6 SelectIO Resources" pdf) Won't the termination be wrong if the port is used as an source, as it will be terminated twice, once at the source and once at the sink?
  12. hamster

    DVI Receive on Zybo

    I've been doing a bit of playing around with DVI-D lately (see http://hamsterworks.co.nz/mediawiki/index.php/HDMI_Input) on Spartan 6, so if you are desperate to get started maybe it will help. The source project should easily port through to Vivado, but I haven't started looking at the 7-series SERDES to see how hard it will be to tweak the "input_serailizer.vhd" and the required clocking. It might just work :-)
  13. Plenty of ways...but your question is a bit vague. Here are a few options. - You can supply an logic-level clock to one the PMOD pins, and use that as the clock signal in your design. - You can use the on-board clock and make a fractional clock generator (which will have pretty bad jitter, as the resolution is limited by the clock rate of the fractional clock generator) - You can use a "clock enable" signal that is not asserted on every clock cycle, to slow your design down - You can use a Digital Clock Manager (DCM) to generate quite a few different clocks, and then switch between them (perfect if all the clock rates are known in advance) - You can use a DCM_CLKGEN, where you can reprogram the DCM's multiply or divide frequency on the fly (e.g. to switch a large amount of logic between a few fixed clocks) .... Or you can do a mix of the above techniques! It really depends on WHY you want a variable clock, and HOW you intend to use it... what are you trying to do?
  14. Last night I was wondering if you could use the analog VGA port on my Basys3 to generate useful high frequency (3MHz - 30 MHz) signals. Well it turns out you can, as long as you are not too fussy about noise, which is at about -32 db. See http://hamsterworks.co.nz/mediawiki/index.php/DDS_via_a_VGA_port for details
  15. My name is Mike, and I've developed a bit of an obsession with FPGAs. You might be able to find some project ideas or inspiration on my WIki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_Projects I'm always happy to talk FPGAs, so feel free to drop me an email sometime
  16. Hi LariSan, I've had my Basys3 for about a week, and I like it lots - it is a much, much bigger faster FPGA than the Basys2. Is there any reason why the DVD-style cases were discontinued? I quite like being able to keep a board in my laptop bag, and I imagine that EE or CS students found this a great feature.
  17. I've just finished porting the Bombjack FPGA implementation from a Spartan 6 board to my Basys3 board. As it was my first attempt at anything meaningful with Vivado the code base is a bit messy, but if anybody wants a copy just drop me a message. The only changes required were to replace the DCM_CLOCKGEN with a MMCM, and to look into some weird timing problems as old arcade games did not us a fully synchronous design. However please note - I can give you the hardware design files, but I am unable to redistribute the actual ROM images that are required to implement the game.
  18. hamster

    PMOD as GPIO

    Hi Alvin, Have you added a constraint to bind the signal to the physical pin? Just giving it the same name as the pin isn't enough... The master constraint file for the Nexys4 can be grabbed from http://www.digilentinc.com/Data/Products/NEXYS4/Nexys4_Master_xdc.zip, and then you will need to add the lines like this to your projects Implementation Constraint file. NET "JC0" LOC = "K2" | IOSTANDARD = "LVCMOS33"; This will cause the signal JC0 to be connected on the "K2" pin on the FPGA package, Mike
  19. hamster

    Oscilloscope for Nexys 4

    Hi JC2694, The short answer is you want to get the best scope that your budget allows. But for a more complete answer, the document you want is http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf - in particular table 15. "DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14) is between 960Mb/s and 1250Mb/s, depending on speed grade." However, you are very unlikely to use these speeds (or be able to afford a Oscope that can work at them). There are tools like Xilinx's ChipScope that allow you to see what the signals look like on the inside of the the FPGA.