• Content Count

  • Joined

  • Last visited

  • Days Won


hamster last won the day on January 7

hamster had the most liked content!

About hamster

  • Rank
    Overly helpful
  • Birthday 08/23/1969

Contact Methods

  • Website URL

Profile Information

  • Gender
  • Location
    New Zealand
  • Interests
    Electronics, FPGAs, MtBiking, Road Cycling, Linux....

Recent Profile Visitors

6483 profile views
  1. On this topic I've been making an audio DSP board using the CMOD A7, where additional noise is a real pain. My initial prototype board had some audio noise problems - I couldn't hear it but I could measure it. I initally thought was due to the CMOD-A7 and could not be fixed, but eventually put down to quite a few different causes: - I had nearly shorted the output of one of the DAC to GND, which as causing spikes on the power rail. Once fixed things were a lot better, but not perfect/ - I had not made any real attempt to stitch the top fill to the ground plain on the bottom - after all it was a hack. - I didn't have any series resistors in the I2S lines. I added 50 ohm ones (just picked a random value out of the air - might look at this again) - I had a few capacitor bodges standing up in the air, which could only make things worse - I was measuring very close to the FPGA, with a high impedance scope probe So I addressed all of these in the next prototype, and made up a test jig allowing me to measure 30cm from the board and things are much better - to the point I can't reliably measure any additional noise in the audio band. I guess what I am trying to say is that even with just one GND pin the CMOD-A7 can be part of a low noise audio system, but you have to put some extra thinking and work in to make it happen. This may or may not be of use to your use-case.
  2. The last of the parts came in and the new board is up and running. Here's the old and new boards side by side, and spectrum of a 10kHz test tone going from the ADC, through the FPGA and then DAC (top = new board, middle = old board, bottom = no board in the loop. The additional work I did on grounding on the PCB has paid off, with a very good noise floor - better than I can measure with the tools I have to hand.
  3. I just had a look at the J1b source, and saw something of interest (well, at least to weird old me): 4'b1001: _st0 = st1 >> st0[3:0]; .... 4'b1101: _st0 = st1 << st0[3:0]; A 32-bit shifter takes two and a half levels of 4-input, -2 select MUXs per input bit PER DIRECTION (left or right) and the final selection between the two takes another half a LUT, so about 160 LUTs in total (which agrees with the numbers above) However, if you optionally reverse the order of bits going in, and then also reverse them going out of the shifter, then the same shifter logic can do both left and right shifts. This needs only three and a half levels of LUT6s, and no output MUX is needed. That is somewhere between 96 and 128 LUTs, saving maybe up to 64 LUTs. It's a few more lines of quite ugly code, but might save ~10% of logic and may not hit performance (unless the shifter becomes the critical path...).
  4. The toolchain is pretty simple to build but takes a while - for me it was just clone https://github.com/riscv/riscv-gnu-toolchain, make /opt/riscv (and change ownership), then run './configure' with the correct options, then 'make'. There are a whole lot of different Instruction set options and ABIs, so I definitely recommend building from source rather than downloading prebuild images. At the moment I haven't included any of the stdlib or soft floating point. I'll add that to the "todo someday" list.
  5. I've just posted my holiday project to Github - Rudi-RV32I - https://github.com/hamsternz/Rudi-RV32I It is a 32-bit CPU, memory and peripherals for a simple RISC-V microcontroller-sized system for use in an FPGA. A very compact implementation and can use under 750 LUTs and as little as two block RAMs - < 10% of an Artix-7 15T. All instructions can run in a single cycle, at around 50MHz to 75MHz. Actual performance currently depends on the complexity of system bus. It has full support for the RISC-V RV32I instructions, and has supporting files that allow you to use the RISC-V GNU toolchain (i.e. standard GCC C compiler) to compile programs and run them on your FPGA board. Here is an example of the sort of code I'm running on it - a simple echo test:, that counts characters on the GPIO port that I have connected to the LEDs. // These match the address of the peripherals on the system bus. volatile char *serial_tx = (char *)0xE0000000; volatile char *serial_tx_full = (char *)0xE0000004; volatile char *serial_rx = (char *)0xE0000008; volatile char *serial_rx_empty = (char *)0xE000000C; volatile int *gpio_value = (int *)0xE0000010; volatile int *gpio_direction = (int *)0xE0000014; int getchar(void) { // Wait until status is zero while(*serial_rx_empty) { } // Output character return *serial_rx; } int putchar(int c) { // Wait until status is zero while(*serial_tx_full) { } // Output character *serial_tx = c; return c; } int puts(char *s) { int n = 0; while(*s) { putchar(*s); s++; n++; } return n; } int test_program(void) { puts("System restart\r\n"); /* Run a serial port echo */ *gpio_direction = 0xFFFF; while(1) { putchar(getchar()); *gpio_value = *gpio_value + 1; } return 0; } As it doesn't have interrupts it isn't really a general purpose CPU, but somebody might find it useful for command and control of a larger FPGA project (converting button presses or serial data into control signals). It is released under the MIT license, so you can do pretty much whatever you want with it. Oh, all resources are inferred, so it is easily ported to different vendor FPGAs (unlike vendor IP controllers)
  6. Clip the oscilloscope ground lead to the probe tip, and wave it near the board.. Tell us what you see...
  7. WAV files are the simplest to work with. 1. The WAV file have s small header on it, then they are all raw sample data, usually stereo pairs of 16-bit signed numbers. Just write a small program in your favorite scripting language to print out data after about 64 bytes. 2. For phone-quality audio, you need bandwidth of 300Hz to 3kHz. - this needs around 8000 samples per second, and about 8-bit sample depth . You could use some u-law or a-law compression to increase dynamic range (https://en.wikipedia.org/wiki/Μ-law_algorithm) 3. - 8 kilobyes per second, if you play raw 8-bit samples. Oh, and to convert data from a WAV file to lower sample rates (e.g. from 48kS/s to 8kS/s) you can't just drop 5 out of six samples - you need to first filter off the frequencies greater than half the target sample rate. It's not that challenging to actually do in code (usually just a couple of 'for' loops around something like "out[x] += in[x+i] * filter[j]') but generating the magic values for the filter can be interesting.
  8. The "DC and Switching characteristics" tells you the delays in the primatives, but can't tell you the routing delays. The only way to truly know it to build the design in Vivado, and then look at the timing report. Inference of DSP blocks and features is pretty good as long as your design is structured to map onto the DSP slices. There are little gotchas like not attempting to reset registers in the DSP slice that don't support it. Skim reading the DSP48 User Guide will pay off many times over in time saved from not having to redesign stuff over and over to help it map to the hardware.
  9. My views - if you want to learn low-level stuff (eg. VHDL/Verilog coding), buy a board with lots of buttons, LEDs, switches and different I/O over a more application specific development board. I think think that the Basys3 is pretty good for this and better than the Arty. Once you have sharpened your skills, then look for a board that will support your projects. If you want to initially work at a systems level, using IP blocks and so on, then look for a board that has interfaces that supports your area of interest. Debugging H/W when you are also debugging FPGA designs is no fun. A Zynq based board (e.g. Zybo) would be good, as it already a CPU, that is much better (faster, less power, better features) than a CPU you could implement in the FPGA fabric. Just be warned that with a Zynq system the SDRAM memory is usually on the far side of the processor system, so you don't get direct access to it - you need to access it over an AXI interface and compete with the CPU for bandwidth.
  10. hamster

    Dividing in Verilog.

    It may well do, but not knowing *all* the details of what you are doing means I can't offer you useful advice.
  11. Seen the problem. You need to define both o1[0] and o1[1] in your constraints, as o1 is a vector of two signals. At the moment you are trying to attach both signals to the same pin, hence the error. Ditto for o2, o3 and o4.
  12. hamster

    Dividing in Verilog.

    If you are dividing by a constant to can multiply by the inverse. If you only have a small number of different divisors you could consider a lookup table of inverses. Otherwise you need to implement a binary division algorithm yourself, to meet your throughput and latency needs. Division by arbitrary numbers is quite expensive - best avoided if at all possible.
  13. Are you showing us all of the file? What does the top level of your design look like? Do you have any other XDC files in your project?
  14. Oh, found the source of some of the noise, and it wasn't the FPGA (phew). I had inadvertently bodged the output RF filtering capacitor to the wrong side of the output resistor causing it to pull lots of current when switching. A bit more bodging to the correct side and it is now a lot better. Now if I short out the inductors on the DAC's power supply I now see the FPGA noise, and when I remove the short the noise goes away.