hamster

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About hamster

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  • Birthday 08/23/1969

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  1. Of, you are using the button as a clock signal because you have inferred a latch. There are some paths through the logic in the combinatorial block that do not set nextState.
  2. Your clock signal is not connected to a pin that connects directly to the FPGAs internal cocking resources. If you add the constrain mentioned in the error report the tools will make it work, but due to the extra 'bits and pieces' requires to make this happen performance might be reduced (eg the clock may have extra jitter). Should be fine unless you are doing a high performance design. PS using the button as a clock signal is a bad idea...
  3. A reasonable sized FPGA should be able to absorb your CPU designs and the Nexys Video is a pretty capable board. Is there any chance of including a "show_utilization -hierarchical" where we can review things? My feeling is that with a bit of though a lot of FFs and LUTRAMs could be revised to use more efficient, denser resources. Have you done much reading of the 7-series user guides, and the style guides that help you to write code that infer the most effective resources?
  4. Because I am quite happy to use a whole block of RAM rather than debugging indexing and sign-flipping code... It's actually one full cycle (half positive, half negative). It is jsut a column from a Google docs spreadsheet https://docs.google.com/spreadsheets/d/13srKHRNCD2dfbMglMvvCUESHR23kHWlzAJ24MJ_erzc/edit?usp=sharing I could have also got away with just one quadrant, but then it would be more 'active' code on what I'm not interested in playing with
  5. I can't see the latching issues, but agree that if the +/-2048 was a separate signal, then the code could be simplified quite a bit... however, the optimizer should be doing that at the moment. "Premature optimization is the root of all evil" and so on. One other finer point. As currently written +full scale value will generate a stream of all ones output but a -full scale won't generate all zero outputs, but a zero value gives a perfect 50:50 mix of ones and zeros. Others might need it that -full scale gives all zeros, and +full scale gives all ones, but a zero value will give sligh
  6. @Dan, I managed to find the 'average' option rather than 'decimate' which has stopped high frequency noise showing up in the spectrums, giving a more reasonable noise floor.
  7. BASYS3 + PMOD Breadboard + Analog Discovery 2. It was just a hack, so the table was a quick formula in a spreadsheet, yes, I assume the + and - sides are both rounding towards zero causing some asymmetry, but with 11 significant bits that should be somewherere about -60dB at a guess. Most of the noise is just the shoddy physical implementation. Flying wires on a breadboard, on PMODs, just the shielded wires on the AD2 and so on. If I leave a wire hanging around it will pick up most the noise too, maybe 6dB lower than on the channel that is under measurement. This was just a qu
  8. I played around with a 1st and 2nd order 12-bit Sigma Delta DAC implemented on the FPGA. I found the results quite interesting, as the change is pretty simple to implement and the change to the noise on the output spectrum is quite significant, with lowered 2nd harmonic and a much smother noise floor. VHDL code is on GitHub at https://github.com/hamsternz/second_order_sigma_delta
  9. I think of std_logic_vector the same way I would think of digits in a number... the rightmost digit is digit zero. It most likely isn't the best way set things up for this example, but it avoids the need to swap the bit ordering in the ASCII characters. Oh, for the button synchronization... signals take time to get across the chip (speed of light, capacitance and so on), so different parts of the design can see different values for the same signal as it change unless. As you can't control when the user might press the button you have to sample the value of the input signal on the clock
  10. Had a hack at it... tested working on BASYS3 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity msg_repeater is Port ( clk : in STD_LOGIC; btn : in STD_LOGIC; tx : out STD_LOGIC; led : out STD_LOGIC_VECTOR (3 DOWNTO 0)); end msg_repeater; architecture Behavioral of msg_repeater is constant char_t : std_logic_vector (7 downto 0) := "01010100"; constant char_e : std_logic_vector (7 downto 0) := "01000101"; constant char_s : std_logic_vector (7 downto 0) := "01010011"; constant char_space : std_
  11. Away from my laptop at the moment, but they way I would do this: A register sized to hold your clock rate (28 bits for 100MHz). If it is less than the baud_rate, set 'bit_tick' to '1' and add (clock_rate- baud_rate) to the register. Otherwise set baud_tick to '0' and subtract the baud rate from the register. That will give you 'bit_tick' that is 1 for the right number of cycles per second, and allow you to keep everything in the design running in the same clock domain. You also want to have a synchronizer on your button, to make it work reliably. You also have a pr
  12. hamster

    Basys 3 clock question

    IC9 is the 100MHz oscillator. It is on the bottom, just to the right of center. See the bottom left of page 5 of the schematics (on the resources page). Part code is DSC1033CC1-100.0000T
  13. You need a top level module, that describes all the signals that are connected to your FPGA. It will then contain all you synthesiable VHDL components that make up your design, and describes how they are connected to the each other and the outside world.
  14. Ok - here's how to drive the seven segments, from 1000 feet up. You need to have the constraints for the segments and the anodes for the display. See the board's reference manual and master UCF file for them. ##7 segment display #set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca #set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb #set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc #set_property -dict { PACKAGE_PIN K13 IOSTANDARD L
  15. Oh, here is a paper that might provide some insight... have a search for "Efficient FPGA Implementation of the RC4 Stream Cipher using Block RAM and Pipelining filetype:pdf" (The URL was too long to post here).