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About jasonbla20

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  1. Thank you for your reply. In my video pipeline, I'm using AXI VDMA -> (decoder) -> AXI stream to video out -> rgb2vga -> vga display. With all these cores being on the AXI4 bus, I assumed that the decoder must be also. I thought the AXI bus was the high performance bus on the zybo? I did use the top module of the decoder hdl as the top module of the AXI4 peripheral. Can you explain why this is incorrect? Thank you
  2. Hello, I downloaded the source HDL for a h.264 decoder from opencores.org. I'm trying to integrate this core into a video pipeline using the Zybo board. In order to use this core, I need it to be on the AXI4 bus. I'm trying to package the IP as an AXI4 peripheral using the Create and Package IP wizard, however I get errors. I've searched the Xilinx documentation for help as to what these might mean, buy I haven't found anything super helpful. My Questions: 1. Is it possible to package this core as an AXI4 peripheral? 2. Can anyone explain, or point me to some documenta
  3. Thanks for your reply. I will check out those linked tutorials when I have a moment. I believe the nova_tb.v is the top module of the verilog project. Here a diagram from the documentation:
  4. Hello, I downloaded the verilog source files for a H.264 Decoder from opencores.org; I'm trying to integrate this decoder into a video pipeline on a Digilent Zybo board. However, when I try to package this IP in Vivado 2016.2, the GUI shows there is no ports. I'm able to successfully package it, but it is useless because there is no i/o. I've attached a few pictures from the Create and Package IP wizard to illustrate what I'm talking about. If I click the port import dialog, as shown in the picture, nothing happens. Does anyone have any suggestions as to how I can successfully impor
  5. I have the display working now; I must have interpreted the jumper settings on jp2 wrong. Thank you so much!
  6. jasonbla20

    No Ouput PMOD CLS

    Hello, I'm using the PMOD CLS, following the instructions found at https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start My issue is that I cannot get any output on the screen - on power on, I see two vertical lines displayed, so I know it's powered. I have the PMOD connected to the JC port in my schematic and physically on the top row of the JC port on the board. I have the CLS configured with JP2 Jumpers MD1 and MD2 are closed, MD0 is open. JP1 jumper is open, however I've tried it open,closed and across RST. I've copied the source files (
  7. jasonbla20


    Thank you very much!
  8. jasonbla20


    Hello, I'm trying to learn how to use the PMOD CLS display on the ZYBO board using Vivado 2016.2. I'm following the tutorial found here:https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start. I've attached a picture of my block design. I have three questions: 1. On the PMODCLS_v1_0, what should the frequency of the ext_spi_clk be? 2. Looking though the documentation on the boards PMOD connectors, I see that UART, SPI, and I2C communication happens on the MIO pmod which is the JF pmod. When choosing which pmod to connect to the CLS in vivado, I only