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About lvoudour

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  1. Of course, you're right, thanks Alex
  2. Thanks, it makes sense now. By the way which part of the clocking infrastructure does it violate? I'm doing a manual dvi implementation right now and I'm pretty sure I can generate a ~750 MHz ddr clock without violating the MMCM vco Fmin/max limits (unless I'm reading something wrong from the datasheet) That's great. Thanks!
  3. *UPDATE* Going the "vivado way" (create project, generate bitstream, export hardware and launch SDK) it works great! It still bugs me why the SDK way doesn't work (tried it again afterwards still no luck). Maybe one of your engineers can take a look at it? For those in ubuntu linux take note that I run to all sorts of problems until I could successfully run the create_project.tcl in vivado, mainly missing libraries. In the end I had to comment the last lines in the script # if {[llength $sdk_list] != 0} { # exec xsct -eval "setws -switch ../sdk; importproject ../sdk" # } because xsct caused vivado to hang. If anyone has any questions (or any solution to the last part) please tell me By the way, I tried it in windows 10 as well but I have vivado 2017.3 installed and I gave up because I couldn't build the application. Steps I followed: Downloaded the latest digilent vivado libraries Updated xilinx ip cores Recreated the hdl wrapper Fixed the location of some pins that for some reason were incorrectly assigned Regenerated the fsbl and the demo bsp Tried different toolchains (arm gnu v7 and v8) because it couldn't find the default one Got ld errors I couldn't resolve and just gave up Anyway, I'll stick to 2016.4 which seems to work for now Question 2 still stands: Is 1080p in spec? If not, shouldn't there be a note in the project wiki? Thanks
  4. Hello, I just got the Arty Z7 and I was trying the HDMI out demo. I followed the SDK handoff guide, downloaded the bitstream and run the demo. I can see the serial output and can enter commands, but I get a "no signal" on my monitor no matter the resolution. Checked and rechecked the connectors to no avail. I tested my monitor's HDMI input with the same cable on a raspberry pi and it works fine. I'm running Vivado/SDK 2016.4 on Xubuntu 17.1 Any ideas? Question 2: Is 1080p output really in spec for Z7? The zynq datasheet shows 950Mbps as the max for LVDS OSERDES Thanks
  5. Indeed, but for what is worth I wouldn't even bother with any such pmod application if I hadn't read through this discussion. Anyway, sorry for hijacking the thread
  6. I was wondering that myself for the Arty "high speed" PMODs, so I got a rather inexpensive HDMI Transmitter Expansion Module from numato (since digilent doesn't offer any HDMI PMOD modules). It has two 2x6 pin headers but the pin order is not really compatible with the Arty differential pairs nor is the distance between the two headers the same, so I had to use jumper wires (run-of-the-mill, 200mm). I used your Arty 1080p code. With the naive approach (connect and pray) max resolution all I could get was 720x480p (27MHz pixel clock). Anything with a higher pixel clock would simply fail. After giving each pair of wires a few twists though, I was able to get 1280x720p @60Hz (75 MHz). That's 750Mbps per pair, which is quite impressive. I even jiggled the wires and left my phone next to them (called a couple of times too ) but it didn't go out of sync. There could bit bit errors, but there was no obvious picture degradation (not that my eyes are any serious BER test). Couldn't get 1080p though. Maybe if I snip the wires shorter, but it's out of spec anyway and 720p is more than enough to play with. Zygot's challenge is very interesting by the way (as is the discussion in this thread), unfortunately I only own this Arty at the moment. It would be nice if the people at digilent could do the test with various boards and tell us what the max achievable rate is (pmod documentation is rather lacking in this area). It's still nice to see this kind of performance
  7. All right, thank you Jon that's probably what I'm going to do (oversample and average) Regards, Lymperis
  8. Hi Jon, You can definitely sample faster than 600 samples/sec, the problem is the faster you go the larger the accuracy error because of the big settling time. I'd be really interested on your engineer's input as I'm definitely not an expert in this area. By the way, another thing I noticed is that the INA199A1 datasheet lists the maximum output capacitive load as 1nF, but the Arty has a 10nF cap. I don't know what the effect is, but maybe it's worth mentioning it too to your engineer. Thanks again, Lymperis
  9. @silverwolfman Synthesized your code in 14.7 (for a spartan 6 device, but it shouldn't matter). The "Result of 32-bit expression is truncated to fit in 1-bit target" is on line 11 of the code you posted here (not line 31) assign clk_o = (rst_n_i == 1'b0)? 0 : clk_o_s; but that's because the 0 assignment is treated as an integer. If you change it to: assign clk_o = (rst_n_i == 1'b0)? 1'b0 : clk_o_s; the warning goes away. Your synthesis report says line 31 because the CLKDIVIDER.v in the zip file also contains a comments header which pushes the aforementioned line to 31 Simulation in modelsim also works as expected, just a note though: The resulting frequency won't be Fclk / divider (if that's what you intended) but Fclk / 2^(divider+1) Regards, Lymperis
  10. Hi Jon, thanks for the reply. Could you please elaborate on the problems you've faced with the XADC? Were there related to the power/voltage/current monitoring circuits on the Arty? Since I can't find any projects online using those circuits I'll go ahead and try to test them myself. Unfortunately, I bought the Arty for personal use and I don't have the proper equipment at home to validate their accuracy/error. Anyway, I'll post here any findings for future reference in case someone else wants to use them Regards, Lymperis
  11. Hello, I got an Arty board about two months ago and I'd like to use the power supply monitor feature. My main question is: "what's the appropriate sampling rate" Never used a 7 series FPGA before so I started reading through the XADC user guide [UG480] and the Driving the Xilinx Analog-to-Digital Converter [XAPP795] note. From what I understand (correct me if I'm wrong): Both inputs must be set to unipolar The XADC should be operated in simultaneous sampling mode to sample both voltage and current at the same time No auto-calibration in this mode. Calibration is done once at power-on The sampling rate should be low enough to cover the settling time of the analog input Looking at the respective circuit and assuming 12-bit accuracy, the settling time for the voltage sensing inputs [XAPP795,pp.2-8], [UG480,pp.79-80] is roughly tset = 9.01 * (8.33K + 8.25K + 1K + 1K) * 10nF ~= 1.67ms which implies sampling rates < 600 samples/sec if I don't want any gain errors. That's fine, but the problem is the XADC cannot be used for other, faster inputs we can't directly drive the XADC with the 100MHz board clock anymore, because the maximum ADCCLK divisor of 255 implies a minimum ~15Ksps/sec rate (not that big of an issue, plenty of PLLs in the chip - just worth mentioning) The few options I see are: Forget about mixing monitoring and higher rate signals in the same design Lower the bit accuracy and use averaging Live with the error at higher rates and use averaging Am I missing something here, do I have this whole thing completely wrong? Has anyone successfully used the monitor inputs in the Arty? (couldn't find anything online) Thanks, Lymperis