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  1. So when i have create a peripheral in vivado in which my slave peripheral is axi lite and my master transaction is axi full, i can connect all the input port of slave peripherals connected to the master output, and only the output pins of the slave need to be connected by the master input?? i.e only for all the slave ports of the below figure.
  2. hello friends, how can i create a axi lite transaction to a axi full transaction , my slave transaction should be axi lite and my master transaction is axi full , i have created a peripheral in vivado in which my slave peripheral is axi lite and my master transaction is axi full, but when i port map, slave peripherals to master peripherals my addr bus of the slave peripheral is 4 bit and my master bus is of 32 bit bus. so im not able to port map it and create the exact transaction which i wanted kindly help ?? is there any other way?
  3. hello friends, can we write to the block memory generator through port A by axi interface and read to the same block memory generator through port B by native interface???
  4. when i use the trafic gen in custom mode in axi4 mode slave peripheral is generating, but i think the purpose of traffic gen is generating the data by itself , since slave peripheral is generating can i give counter data to it??
  5. Ok fine il try to implement this way, lastly the data that is generating from traffic generator is random numbers, can it generate a sequetial data like counter, or can i give a counter data and verify it in SDK using traffic generator? i have used trafic gen in high level traffic in data mode.
  6. hai [email protected], i actually want to test axi gpio, i have already tested the transaction between the axi traffic gen to bram ,,, by exporting the design to SDK and reading the address, just want to test the axi gpio hence i am giving gpio input to axi traffic generator through axi gpio, and wanna enable it to start , stop of traffic generator. btw hw do i give start stop enable pins from zynq to traffic gen, where do i need to select it in zynq?.
  7. 1) can we connect axi gpio signals which is on the slave side to the axi traffic gen start, stop bits, which is on the master side of the axi interconnect, how can we do it??, since my axi gpios width cannot be a single bit which can be given to the axi traffic gen start stop bits. 2)I want to enable my axi traffic gen, on start bit from the axi gpio and write the data into the axi register which is on the slave side?? kindly help me I'm beginner to vivado model based design. i have build design as per the image attached on addition to this, i want to add the above features to it as