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About GreatGBL

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  1. Hello, I solve it, the problem is not the communication... The Microphone output the negative voltage and the ADC can't convert it, so all the negative voltage data lost, and at that time I did not know that.. After support +5V DC voltage on each microphone, the negative voltage issue solved, and I test the data transmission again, only 3% data lost , it is acceptable. Thanks for your help during those time !!!!
  2. But how LFSR solve those issues? LFSR just generate a sequence of Pseudo-random code
  3. Hello, I want to know why I can't use the counter in the test, my understand is that a bit of counter may be chaned in the communication. For example , a 8-bit counter send 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 (4) While a noise interfere the MSB, the receiver got 1000 0100 (132) and I will say, Aha, there are 132-4 = 128 data lost It is like that issue ?
  4. OK, thanks for your help, I go to using LFSR test it again. Sorry for my ignorance in high frequency communication
  5. OK, your means using Gray code is much better ? I go to try
  6. Thanks for your code, but I dont understand why a counter is not a good test signal? It is much readable and easy to generate, the value of counter send to Zedboard by binary and send to PC by decimal.
  7. Vivado 2016.1 See the counter example, the received data should be 0,1,2,3,4,5,6....
  8. Hello, I tested it today. For easy read the data, I use the counter to generate the data, and transmit it to Zedboard in 100MHZ, 50MHZ and 25MHZ respectively. The Zedboard read the GPIO continually, save it into DDR3 memory if the current data is not same as the previous one. Then, the Zedboard use UART way transmit all the data to PC, because I used DD3 memory, so there is no any data lost by UART. The result shows below.. Ideal: Zedboard will receive : 1 2 3 4 5 6 7 8 9 ..... 100MHZ : Sorry I forgot to copy the raw data , but I remember there are 128 data lost between each received data. 50MHz: -Read the data from memory, numbers: 135776 -- 21 83 145 222 269 331 392 453 515 577 638 702 761 822 884 945 1007 There are approximatly 62 data lost between each received data. 25MHZ: --Read the data from memory, numbers: 101621 -- 8406774 8390342 8390390 8406774 8390342 8406774 There are approximatly 48 data lost between each received data.
  9. Because when I first touch the Zedboard, I build the IP core and AXI interface, I found there are using Verilog language. It is ok to mix the Verilog language and SystemVerilog language together and run on Zedboard ? But it doesn't matter, I will go to try LFSR to check whether data losts. The other problem is the data lost on the channel between ADC and Basys3 due to other reason.
  10. Ok, it is a good idea, I will test it during this week!
  11. AHa, because the Zedboard using Verilog language while I only know the SystemVerilog language which using on Basys3, I can't write complex code like SPI protocol on the Verilog language.
  12. That is the flow diagram of my project The ADC has 10Mhz as system clock, if the Basys3 needs receive 24bits data, it need 24*(1/10M) second. Then the Basys3 send the data to Zedboard immediately. So the frequency between two board is 1/(24*(1/10M))=416,667 Hz = 0.416MHz. .Theoretically if the frequency of Zedboard transmites the data from PL to PS Is 1MHz, it is enough. While there are approximately 20% data lost. I dont know the reason. Ok, I find a method, How aboult add a FIFO buffer in the BASYS3. the FIFO can save 8 data inside. When the Zedboard has been read one data, the read SP of FIFO buffer add 1, but how the Basys3 know the Zedboard has been read is a problem...
  13. Yes, I used the PS layer to read the GPIO (at Pmod) on the Zeboard. I use another FPGA board, Basys3, connect to the Zedboard Pmod pins. The Basys3 will send approximate 1024*8*4*24 bits to the Zedboard at every 240 rising of the system clock (Note the Basys3 system clock frequency is 100MHz). Then, I checked the Zedboard, it successfully receive only 800*8*4*24 bits, in other words, there are 20% of data lost.. On the other hand, sometime it can successfully receive 1000*8*4*24 bits so there are only 3% data lost, but it only happen few times..... Then, a enable signal never be received by Zedobard, it sent by Basys3 at every 240 rising of the system clock, but the duration of it only a 1 clock of the Basys3 system clock, I guess the reason of why Zedboard can't receive that is the duration of the signal is small. But Theoretically , If Zedboard has 667Mhz to read the GPIO, it should to receive that. So what should I do to reduce the lost data percentage? 20% is too lager really for my project.. Thanks for your help, Kind regards, GreatGBL
  14. Hello, my project has a high frequency operation on the GPIO on the Zedboard. I want to ask how the Zedborad (Or general FPGA board) read the value from the GPIO ? On the every rising clock? I found that the Zedboard system clock is 667MHz, it means in 1 second the Zedborad read the GPIO value 667M times? Thanks for your help.