Hendrik

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  1. Looking for a quick small script(Matlab or Python) to test serial communication between the ProMx7 and Matlab,can anyone help? Thanks H
  2. Hi Dan, Thanks tested my filter component and that is working fine the issue is handing the data off from the XADC to the filter. See error message below:
  3. I have created a FIR filter in VHDL and interfaced the filter with the XADC....was able to build a bit stream.When I test this I don't seem to get the proper output waveform,WHY? SEE CONFIG below. 1.XADC config 2.adc module 3.toplevel ---XADC config MODULE1 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; Library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity xadc_wiz_0 is port ( daddr_in : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port den_in : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port di_in : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port dwe_in : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port do_out : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port drdy_out : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port dclk_in : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port reset_in : in STD_LOGIC; -- Reset signal for the System Monitor control logic vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6 vauxn6 : in STD_LOGIC; busy_out : out STD_LOGIC; -- ADC Busy signal channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs eoc_out : out STD_LOGIC; -- End of Conversion Signal eos_out : out STD_LOGIC; -- End of Sequence Signal alarm_out : out STD_LOGIC; -- OR'ed output of all the Alarms vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair vn_in : in STD_LOGIC ); end xadc_wiz_0; architecture xilinx of xadc_wiz_0 is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "xadc_wiz_0,xadc_wiz_v3_3_2,{component_name=xadc_wiz_0,enable_axi=false,enable_axi4stream=false,dclk_frequency=100,enable_busy=true,enable_convst=false,enable_convstclk=false,enable_dclk=true,enable_drp=true,enable_eoc=true,enable_eos=true,enable_vbram_alaram=false,enable_vccddro_alaram=false,enable_Vccint_Alaram=false,enable_Vccaux_alaram=falseenable_vccpaux_alaram=false,enable_vccpint_alaram=false,ot_alaram=false,user_temp_alaram=false,timing_mode=continuous,channel_averaging=None,sequencer_mode=off,startup_channel_selection=single_channel}"; signal FLOAT_VCCAUX_ALARM : std_logic; signal FLOAT_VCCINT_ALARM : std_logic; signal FLOAT_USER_TEMP_ALARM : std_logic; signal FLOAT_VBRAM_ALARM : std_logic; signal FLOAT_MUXADDR : std_logic_vector (4 downto 0); signal aux_channel_p : std_logic_vector (15 downto 0); signal aux_channel_n : std_logic_vector (15 downto 0); signal alm_int : std_logic_vector (7 downto 0); begin alarm_out <= alm_int(7); aux_channel_p(0) <= '0'; aux_channel_n(0) <= '0'; aux_channel_p(1) <= '0'; aux_channel_n(1) <= '0'; aux_channel_p(2) <= '0'; aux_channel_n(2) <= '0'; aux_channel_p(3) <= '0'; aux_channel_n(3) <= '0'; aux_channel_p(4) <= '0'; aux_channel_n(4) <= '0'; aux_channel_p(5) <= '0'; aux_channel_n(5) <= '0'; aux_channel_p(6) <= vauxp6; aux_channel_n(6) <= vauxn6; aux_channel_p(7) <= '0'; aux_channel_n(7) <= '0'; aux_channel_p(8) <= '0'; aux_channel_n(8) <= '0'; aux_channel_p(9) <= '0'; aux_channel_n(9) <= '0'; aux_channel_p(10) <= '0'; aux_channel_n(10) <= '0'; aux_channel_p(11) <= '0'; aux_channel_n(11) <= '0'; aux_channel_p(12) <= '0'; aux_channel_n(12) <= '0'; aux_channel_p(13) <= '0'; aux_channel_n(13) <= '0'; aux_channel_p(14) <= '0'; aux_channel_n(14) <= '0'; aux_channel_p(15) <= '0'; aux_channel_n(15) <= '0'; U0 : XADC generic map( INIT_40 => X"8116", -- config reg 0 INIT_41 => X"310F", -- config reg 1 INIT_42 => X"0400", -- config reg 2 INIT_48 => X"0100", -- Sequencer channel selection INIT_49 => X"0000", -- Sequencer channel selection INIT_4A => X"0000", -- Sequencer Average selection INIT_4B => X"0000", -- Sequencer Average selection INIT_4C => X"0000", -- Sequencer Bipolar selection INIT_4D => X"0000", -- Sequencer Bipolar selection INIT_4E => X"0000", -- Sequencer Acq time selection INIT_4F => X"0000", -- Sequencer Acq time selection INIT_50 => X"B5ED", -- Temp alarm trigger INIT_51 => X"57E4", -- Vccint upper alarm limit INIT_52 => X"A147", -- Vccaux upper alarm limit INIT_53 => X"CA33", -- Temp alarm OT upper INIT_54 => X"A93A", -- Temp alarm reset INIT_55 => X"52C6", -- Vccint lower alarm limit INIT_56 => X"9555", -- Vccaux lower alarm limit INIT_57 => X"AE4E", -- Temp alarm OT reset INIT_58 => X"5999", -- Vccbram upper alarm limit INIT_5C => X"5111", -- Vccbram lower alarm limit SIM_DEVICE => "7SERIES", SIM_MONITOR_FILE => "design.txt" ) port map ( CONVST => '0', CONVSTCLK => '0', DADDR(6 downto 0) => daddr_in(6 downto 0), DCLK => dclk_in, DEN => den_in, DI(15 downto 0) => di_in(15 downto 0), DWE => dwe_in, RESET => reset_in, VAUXN(15 downto 0) => aux_channel_n(15 downto 0), VAUXP(15 downto 0) => aux_channel_p(15 downto 0), ALM => alm_int, BUSY => busy_out, CHANNEL(4 downto 0) => channel_out(4 downto 0), DO(15 downto 0) => do_out(15 downto 0), DRDY => drdy_out, EOC => eoc_out, EOS => eos_out, JTAGBUSY => open, JTAGLOCKED => open, JTAGMODIFIED => open, OT => open, MUXADDR => FLOAT_MUXADDR, VN => vn_in, VP => vp_in ); end xilinx; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adc is port ( ADC :in std_logic_vector (1 downto 0); --Vinn :in std_logic; clk :in std_logic; d_rdy :out std_logic; data_out : out std_logic_vector(15 downto 0) ); ---ADC data out to FIR but is called din to FIR end adc; ----------------------------------------------------------------------------------- MODULE2 architecture behavioral of adc is ------------------------------------------------------------------------------------------------------------------- component xadc_wiz_0 is port ( daddr_in : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port den_in : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port di_in : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port dwe_in : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port do_out : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port drdy_out : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port dclk_in : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port reset_in : in STD_LOGIC; -- Reset signal for the System Monitor control logic vauxp6 : in STD_LOGIC; -- Auxiliary Channel 6 vauxn6 : in STD_LOGIC; busy_out : out STD_LOGIC; -- ADC Busy signal channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs eoc_out : out STD_LOGIC; -- End of Conversion Signal eos_out : out STD_LOGIC; -- End of Sequence Signal alarm_out : out STD_LOGIC; -- OR'ed output of all the Alarms vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair vn_in : in STD_LOGIC ); end component ; ----------------------------------------------------------------------------------------------------------------------- signal adc_addr : std_logic_vector (6 downto 0); signal adc_enable : std_logic; signal adc_addr : STD_LOGIC_VECTOR (6 downto 0); signal data_out_1: std_logic_vector(11 downto 0); begin adc_addr <= "001" & x"6"; --adc_addr <= "0010110"; --------------------------------------------------------------------------------- U0 : xadc_wiz_0 port map ( daddr_in => adc_addr, den_in => adc_enable, di_in => x"0000", dwe_in => '0', do_out => data_out ,------------Filter input --do_out(15 downto 4) => data_out ,------------Filter input 12 bits drdy_out => d_rdy, dclk_in => clk, reset_in => '0', vauxp6 => ADC(0), ----------- vauxn6 => ADC(1), busy_out => open, channel_out => open, eoc_out => adc_enable, eos_out => open, alarm_out => open, vp_in => '0', vn_in => '0' ); -- end behavioral;
  4. Hi Jon, This does not have to be in Matlab. The basic question is say I want my script to communicate with the ProMX7. UART3 To what physical port do I need to be connected, the port labeled UART or DEBUG? (I did program the board over the DEBUG port using MPLAB) How can I test comms between the PROMX7 and my PC when using MPLAB as the IDE. Additional info below: Programming with MPIDE: The bootloader on the PIC32 installed my PC see the board at COM9 this is great and is working fine. Programming with MPLAB: If I use the debug port (jumper is set for debug as well) I program the board no errors.When I run the 'mode' command at the cmd prompt in Windows10 I don't see a comport assigned.When I do the same step on the USB port I also see nothing.What is wrong do I need a special driver? Thanks, Hendrik
  5. Hi Arthur ,thanks for the info. Another quick question since I am not able to get a good example.Do you know how to generate a test tone(sine wave) in Vivado?I assume I can create a test bench to do this. I want to feed a test tone say at 1KHz into the XADC of the Basys3 and view the FIR output.Next step is to increase the tone frequency with 1 KHz ,now the test tone is at 2KHz...repeat this process up to 18 KHz. In short how do I simulate analog signals in Vivado. The real test would be to connect the waveform generator to the header and measure output of the R2R DAC. Thanks Hendrik
  6. I have created a FIR filter and would like to run a simulation using sine wave tones at different frequencies to verify the filter frequency response.Any idea how I can do this within Vivado? Thanks H
  7. Thank you Jon...very helpful. My objective is to communicate with the board using Matlab.My program was written in MPLAB and the board was programmed over the debug USB port. Now I want Matlab to communicate with the board using the PIC32 UART3 how do I do this?Do I need to move the cable back to the UART USB port? By the way if the cable is connected to the debug USB port and I then connect to the PC I don't see a COM port assignment. If I use the UART USB port on the board and then connect to the PC I see COM9.(Don't seem to be able to change any of he com parameters,why?) Next,I am trying to figure out how to connect to the ProMX7 board from my Ubuntu virtual machine(guest OS).The Ubuntu is a virtual machine running on Virtual box on my host PC(Windows 10). When I connect the board to my PC using the UART USB port(Promx7 board) I see the board at COM9.I then go into virtual box and set the serial port for Ubuntu to COM1 and the serial port for the host PC to COM9.(everything is enabled ). I then fire up Ubuntu and use the following command to check COM ports. $ dmesg |grep tty but I don't see the board where do I go wrong? Thanks again for the support. H Seem to be tricky. Thanks Hendrik
  8. Very helpful...Thanks you ,I am trying to run my blinky LED now (blink led on pin 51(RD3) of the ProMX7.)...the program compile and load it seem to me I have something wrong with my SFR config. See code below Any quick tips? #include <xc.h> // Load the proper header for the processor void delay(void); int main(void) { //TRISD = 0xFFFC; // Pins 0 and 1 of Port F are LED1 and LED2. Clear or =0b1111111111111100 TRISD = 0xFFFB; //enable RD1 ,RD2 and RD3 to be output bins or using 0b1111111111111000 // bits 0 and 1 to zero, for output. Others are inputs. LATDbits.LATD0 = 0; // Turn LED1 on and LED2 off. These pins sink current LATDbits.LATD3 = 1; // on the NU32, so "high" (1) = "off" and "low" (0) = "on" while(1) { delay(); LATDINV = 0x0003; // toggle LED1 and LED2; same as LATFINV = 0x3; } return 0; } void delay(void) { int j; for (j = 0; j < 1000000; j++) { // number is 1 million while(!PORTDbits.RD7) { ; // Pin D7 is the USER switch, low (FALSE) if pressed. } } }
  9. Hi there, I am trying to connect my Pro MX7 to my PC. 1.I like to program the board using MPLAB IDE. 2.I can see the ProMX7 is connecting to COM port 9.I am not able to see the board in the MPLAB IDE.(attacehd photo) Thanks for the help H
  10. I have completed my FIR filter code on this FIR project (low pass cutoff frequency is 8 KHz) and created a top level design to glue all the building blocks together. 1.The FIR module worked perfect in my simulation. 2.I created a ADC module using the IP core.(I kept it very simple ) 3.I then programmed the Basys3 board. In my test phase I feed the board with a tone 300mV p-p that was generated with a Agilent 33220A waveform generator at 8 KHz.I can see the signal on the DAC output but when I adjust the frequency of the tone to 10 KHz (this frequency is supposed to be attenuated by the LPF) I see the same signal level no attenuation at all.This led me to believe there is something wrong with the signal flow between the ADC module and the filter module. Any Ideas?? I have attached the the top level design and the ADC modules,maybe you can help point out the obvious.By the way the output of the FIR feed the PMOD R2R(DAC 8 bit). Thanks, H. adc.vhd fir_top.vhd xadc_wiz_0.vhd
  11. Hi Dan Yes I did do be honest trying to make sense from the Verilog code pretty new to VHDL myself no experience in Verilog syntax.I have more experience with MCU's,C,Python etc. This is quite a learning curve as you pointed out but I am working it. Thanks for the great support. Hendrik
  12. Thanks for the info very helpful understanding scaling the bits. So I plan to use 2 files XADC.vhl(adc config) and FIR4_tap.vhl (top level) for this design and try to understand how to tie them together. Now,looking at the XADC in continuous sampling mode it takes 22 cycles to perform an A/D conversion.(BUSY go high in the beginning of the conversion phase and low when done with the conversion) So I assume reading through this specsheet I will need to wait 22 ADCCLK cycles (scaled version form clk) then read the VAUXP[0]/VAUXN[0] (Register #0)register.Is this the right train of though? If the "in_data_enable" signal is equal to the "busy" signal in the XADC then I can use this to read the samples stored in the register. I am a little confused how to access the conversion data in the register,can you give me direction on this portion? Thanks, Hendrik
  13. Hi Hamster Thanks for responding to my question.Can you explain this block?How did you calculate the coefficients? signal kernel : t_kernel := (to_signed( 10,8), to_signed( -10,8), to_signed( 255,8), to_signed( -10,8), to_signed( 10,8)); The way I did it was using Matlab, and come up with these coefficients for example: 0.144,0.22,0.25,0.22,0.144 how do I scale them? Thanks, Hendrik
  14. Hi Dan, Sorry for the delay,I got this to work the pin labels I provided in the XDC file was wrong.Thanks again for your guidance. Hendrik
  15. Hi there, I am trying to implement a 4 tap FIR filter on the Basys 3 board.Basically,I feed the ADC with an analog sine wave signal that will get digitized (12 bits) that get fed into the FIR filter( low pass filter 400Hz cut off freq)the output of the FIR filter will drive a 8 bit PMOD DAC. My question is as follows: 1.When I use the on board 12-bit ADC ,do you have some VHDL sample code to show how the A/D conversion would be implemented for this case? 2.During filtering I assume I would multiply my 8 bit coefficient with the 12 bit word from the ADC ending up with a 20 bit word.Now I need to scale this down to 8 bits to drive my DAC.How would I do this in VHDL? Any info would be appreciated.I was not able to find any ADC VHDL sample code for this board if you can provide a link that would be great. Thanks allot H