Hendrik

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  1. 4 tap FIR filter

    Hi Dan Yes I did do be honest trying to make sense from the Verilog code pretty new to VHDL myself no experience in Verilog syntax.I have more experience with MCU's,C,Python etc. This is quite a learning curve as you pointed out but I am working it. Thanks for the great support. Hendrik
  2. 4 tap FIR filter

    Thanks for the info very helpful understanding scaling the bits. So I plan to use 2 files XADC.vhl(adc config) and FIR4_tap.vhl (top level) for this design and try to understand how to tie them together. Now,looking at the XADC in continuous sampling mode it takes 22 cycles to perform an A/D conversion.(BUSY go high in the beginning of the conversion phase and low when done with the conversion) So I assume reading through this specsheet I will need to wait 22 ADCCLK cycles (scaled version form clk) then read the VAUXP[0]/VAUXN[0] (Register #0)register.Is this the right train of though? If the "in_data_enable" signal is equal to the "busy" signal in the XADC then I can use this to read the samples stored in the register. I am a little confused how to access the conversion data in the register,can you give me direction on this portion? Thanks, Hendrik
  3. 4 tap FIR filter

    Hi Hamster Thanks for responding to my question.Can you explain this block?How did you calculate the coefficients? signal kernel : t_kernel := (to_signed( 10,8), to_signed( -10,8), to_signed( 255,8), to_signed( -10,8), to_signed( 10,8)); The way I did it was using Matlab, and come up with these coefficients for example: 0.144,0.22,0.25,0.22,0.144 how do I scale them? Thanks, Hendrik
  4. Basys3 blinking led

    Hi Dan, Sorry for the delay,I got this to work the pin labels I provided in the XDC file was wrong.Thanks again for your guidance. Hendrik
  5. 4 tap FIR filter

    Hi there, I am trying to implement a 4 tap FIR filter on the Basys 3 board.Basically,I feed the ADC with an analog sine wave signal that will get digitized (12 bits) that get fed into the FIR filter( low pass filter 400Hz cut off freq)the output of the FIR filter will drive a 8 bit PMOD DAC. My question is as follows: 1.When I use the on board 12-bit ADC ,do you have some VHDL sample code to show how the A/D conversion would be implemented for this case? 2.During filtering I assume I would multiply my 8 bit coefficient with the 12 bit word from the ADC ending up with a 20 bit word.Now I need to scale this down to 8 bits to drive my DAC.How would I do this in VHDL? Any info would be appreciated.I was not able to find any ADC VHDL sample code for this board if you can provide a link that would be great. Thanks allot H
  6. Basys3 blinking led

    Dan, Yes I did, sorry that was a typo it is "blinker_o".. Still get the same results.Any other ideas??Again the top level program seem to be good I get no errors.(green status). 1.In Vivado(2016.4) where do I see the clk freq assigned for the project?(will it always be 450 MHz)with an oss(100MHz) connected to pin W5 from what I can see on the schematic. 2.Can I send you the XDC and top level design maybe you can run/check it out on your end? Thanks, H
  7. Basys3 blinking led

    Hi Dan, I miss something.I did uncomment the clock and LED lines in the XDC file.Where do I specify the clock freq? ...When I run the simulation I see no clock pulse on the simulation. I replaced the "clk" with "clk_1" and the "led[0]"with "blinker_0" SEE TOP LEVEL BELOW...I did not include the architecture part of the design by the way there is no error in that part of the code I get green light. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity blinker_led2 is Port ( clk_1 : in STD_LOGIC; blinker_o : out STD_LOGIC); end blinker_led2;
  8. Basys3 blinking led

    I tried to do a the blinking LED(at 1 Hz) using VHDL on Vivado 2016.4 with no luck.How should I setup the xdc constraint file to accomplish this,specifically the clock? Thanks, H