kc5tja

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Everything posted by kc5tja

  1. The bill came due because of laziness. Speculation which respects permissions boundaries would have been perfectly fine. It is the fact that CPUs speculate without respect for permissions is what lead directly to Spectre (at least the version that lets you read into kernel memory). That said, my plans are not to go hog-wild with runtime optimizations. An in-order pipeline is a natural, relatively inexpensive performance boost. As I indicated elsewhere, I already have a CPU that runs at 25MHz, but it needs minimum 3, maximum 7 cycles per instruction. I'd like to drop that as much as I
  2. Talk of pipelines is poignant for me, as one of the biggest differences between the Kestrel-2DX's KCP53000 and the Kestrel-3's KCP53010 will, in fact, be that the latter has a 5-stage (maybe 6-stage, not sure yet) pipeline. They should otherwise be software compatible with each other. (The other being that some form of memory protection will be introduced; probably in the form of software-managed TLBs.)
  3. Yes. You are going to fail. You are going to fail hard. You are going to fail so hard, you'll want to flip your table, walk away, curse everything as a waste of time, and never look back. Do all of these things; except, I'd recommend not flipping that table. I find the cursing to be cathartic, and the walking to be mind-clearing. Maaaaaaaybeee try not to be as public about the cursing as *I* have been. I have a reputation. You might not, and it could damage yours. But if you must, curse into an empty room. Scream loud if you must. Get it off your chest; then, get back on the
  4. In order of mention... Status on Kestrel Project. I went back to working on the Kestrel-2 and creating a refinement of this architecture. Instead of the 16-bit stack architecture CPU, however, I replaced the core with my KCP53000 CPU, a M-mode only RV64I RISC-V processor. This has allowed me to expand the design of the computer rather significantly relative to the original design. Kestrel-2's address space was laid out like so: $0000 $7FFF Program RAM $8000 $BFFF I/O space $C000 $FFFF Video RAM The block RAMs were pre-loaded with software to run at synthesis time. There
  5. Hang tight folks; I'm catching up. Will respond shortly.
  6. Thanks! That did the trick. The circuit seems pretty flaky, but it does generate video. If I toggle SW0, the video it produces isn't always aligned with the video edges, but it is stable.
  7. I have the s3e1200 chip.
  8. @sbobrowiczThanks; looking over the VHDL, what I can make of it at least, it's doing what my own state machines are doing. Unfortunately, I was unable to synthesize the project for my Nexys-2 due to errors involving collisions on IOBs.
  9. Two definitions of "it works" are, (1) I can use external RAM for a video frame buffer, and (2) the CPU runs no slower than 2 MIPS. So far, the lack of this chip's ability to adhere to published documentation on its timing parameters forced me to degrade this project's features twice already, and leaves me to believe that the Nexys-2 is simply inappropriate for what I'm trying to do. I'm not willing to do it a third time. I'm evaluating now if my time would be better spent just porting the project to use another FPGA board equipped with real static RAM.
  10. Adding registers to the address and/or data output buses (the only signals w/out registers) introduces a clock of latency. This means now I'd need _seven_ clocks per individual hit to RAM, and it would rule support for 16-color 640x480 displays impossible. Like I said on IRC: accesses to memory must consume no more than six clocks. That is a hard limit. Also, does a Spartan 3 series FPGA even have ODDRs? I don't recall reading about them in the Spartan 3 family documentation. Maybe I missed them.
  11. It works with the BIST code, but that's the only place it seems to work. Under any other circumstances I've attempted to use the PSRAM chip, it has either failed outright to commit writes, OR, has failed to drive the DQ pins on read, as per my bullet list above. The EPP controller is inscrutible to me, I don't know what it's doing or how it does it. Moreover, it's bottlenecked with an 8-bit bus; I really need a 16-bit bus. Per your suggestion on IRC about using an on-chip logic analyzer/scope thing, I attempted to write one that would work for my hardware, but it ends up crashing ISim
  12. Greetings everyone. I'm Samuel A. Falvo II, creator of the Kestrel-3 home-brew computer project. I'm currently using the Nexys-2 board as a development platform, since that's a known-working software/hardware configuration for me. My plan is to migrate to something different/better after I get a working reference model here. Related to this project, I'm completely ineffectual at getting the PSRAM chip to function. I was wondering if someone else has created a 16-bit Wishbone(-compatible/-like) interface to the PSRAM chip that I can re-use in my MPLv2-licensed project. After a mont