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  1. @jpeyron Problem solved ! It is not the problem from xilkernel or timer or memory leakage, it is the problem of gateway setting, so that the port receives so many packets. Thank you very much!
  2. @jpeyron Thank you for your reply! I do use LWIP RAW API example from xilinx, and I don't want to use socket. The whole project is exceed 1MB, so I upload only source code, the hardware binary is generated from example The output I get is: In fact, even without enable echo server, the xemac_add function is enough to generate "unable to alloc pbuf in recv_handler" error, for which xadapter_timer is suspicious in my point of view, but still debugging... Thank you so much!
  3. Hi Mr./Ms., I have successfully make Nexys Video Microblaze server example works following: However, the echo server only works under standalone OS but not xilkernel OS. It gives me the error "unable to alloc pbuf in recv_handler" called from "setup_rx_bds" function, even I haven't telnet the server yet. I have tried: 1. increase heap size 2. increase pbuf_pool_buffer size, pbuf_pool_size 3. increase mem_size, mem_n_pbuf 4. enable jumbo frame 5. increase TX and RX buffer size in axi_ethernet component in vivado The enlarged men size can delay the appearance of this error, but error message still come out and I cannot echo successfully. I guess it is not a pure problem from memory size since standalone works, maybe because the xilkernel is too busy so that cannot catch up with the speed of coming packets. So far the speed of LINKSPEED is also 100MHz as well as sys frequency. I wonder any way can slow down the coming packets ? PS: board is Nexys video, vivado is 16.2, xilkernel is 6.3, lwip is 1.4.1 Thank you very much!
  4. @AndrewHolzer Thank you so much for your help! We finally find the reason why interrupt not work. When generate Microblaze and interrupt controller together, the "Enable Fast Interrupt Logic" will be clicked. But if generate interrupt controller separately, this box will not be activated. This single is the problem. After I disable "Enable Fast Interrupt Logic" in interrupt controller, the interrupt can be caught. Thank you so much again and I can move forward now. Cynthia
  5. @AndrewHolzer Thank you so much for your help! May I know if you can succeed in catching interrupt with under standalone OS? I am trying to figure out if the problem is from software lib or Vivado port. Thank you again! Cynthia
  6. @AndrewHolzer Thank you so much for you effect on helping me! I really appreciate it since this problem have bugged me for 2 weeks. Here are information may help: 1. board is Digilent Nexys Video, board_files is version A.0, Vivado is version 16.2. 2. in SDK, I program the FPGA by Xilinx Tools -> Program FPGA 3. I deleted all sdk and re-explore hardware then re-launch SDK, the same result when running Peripheral SelfTest under xilkernel as before. 4. following figure is the block design, you may notice that I add two interrupts into concat (one is from axi_timer(has 2 timers in default), the other is vivado generated IP with interrupt wrapper). Because I try to test interrupts. MIG is included with 200MHz clk. (referred tutorial: and It may be because I connected axi_timer "interrupt" into Microblaze interrupt controller, so the SDK SelfTest run twice (I am testing it). But I do want to catch interrupt from IP through interrupt controller, but never succeed. No matter I enable exceptions of Microblaze in block design or enable exception in bsp (SDK standalone), interrupt from IP would never be caught. That's my main problem. 5. following is the address mapping in above block design: 6. followings is C code to enable interrupt in SDK I have tried (commented out code is what I tried as well): 7. I auditing the trace port of microblaze as well, realizing the interrupt is not caught, so probably the problem is not from interrupt handler (memory problem) but from interrupt controller, or I miss configure something. Thank you again for being so patience for helping me. The XPS platform and spartan board I used before did not has such problem, now my project get stuck and I have tested with all tutorials related to IP interrupt but failed (except for Ethernet one). Cynthia
  7. @AndrewHolzer Thank you for your help! We added the MIG and recreated the project following tutorial, the result is wired, it still fails but seems run twice and 2rd time the interrupt test fail as well We doubted maybe because the SDK template simulates interrupt and it's not from the real bus, so axi_timer may not work under xilkernel. So we tried this example using vavido generated IP to interrupt: However, the interrupt still not caught by Microblaze. Looking forward for your help! Thank you so much! Cynthia
  8. @artvvb Thank you for reply. This is the error in previous round (because we set run configuration wrong), not this round, I re-test, there is no this error when run. we also test the same project on Nexys 4 board as well. standalone can past avi_timer test but xilkernel cannot. But standalone cannot trigger the customer IP's interrupt although microblaze exception is enabled in bsp and interrupts are enabled and handler is registered. Cynthia
  9. Hi, I am using Nexys Video board and fail to trigger interrupt to Microblaze in SDK. So I generate a basic project with only AXI timer, and test with "Peripheral Test" application for xilkernel in SDK, but the test fails as well. In Vivado: 1. select the board and create a block design. 2. add microblaze with interrupt controller. add axi_timer and uartlite. 3. connection as attached figure: ": 4. enable Microblaze exception. generate bitstream. In SDK: 1. generate bsp for xilkernel, and generate an application of "Peripheral Test" in template, and run. Fail when running "Interrupt Test for axi_timer_0" as shown in figure: In fact, I have tried to interrupt from IP generated by vivado AXI interrupt wrapper, or from customer IP (generated interrupt interface myself), no matter with SENSITIVITY being EDGE_HIGH or LEVEL_HIGH, no matter with concast component or single interrupt, no matter enable exception in bsp or microblaze, neither of them succeed in calling my handler. I believe this is not the problem in software (I register handler and enable all interrupts), and even the template application based on basic components still not work. Did I miss anything? Thank you very much! Cynthia
  10. Thank you very much! I have connected the server as well, initialization is slower than old xilinx SDK I used before (board is 100MHz as well), but it looks ok so far. May I know what cause this warning? Is it matters for further development? since I am developing Ethernet application and want to rule out any wired bug. Thanks again! Cynthia
  11. Hi, I followed the instruction in carefully to create the simple echo server with Nexys video board. The vivado version is 16.2. The Ethernet licence is evaluation version. After creating echo server application and run with SDK , it does not run as expected, the output is as follows: -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back WARNING: Not a Marvell or TI Ethernet PHY. Please verify the initialization sequence link speed: 100 It seems to me the physical interface on the board is not configured right. I tried other lwip application, there is the same problem, so I don't think it is the problem of software or bsp setting. Could you help me ? Thank you very much! Cynthia