B SULLY

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  1. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When lo
  2. I seem to have lost my original Zybo board and am wondering if I purchased a new one, maybe even the Z7 would my existing voucher and Xilinx license work for a new board. I think that is the only think that has survived a recent move, (the voucher and Xilinx Vvado software).
  3. So I have come to the conclusion that My Zych/Zybo dev board has been stolen or misplaced. I am wandering if the "node locked" (OR) "device locked Xilinx Dev packages that I purchased will work I I get a new board of the same make as model. I had the zync 7010. What to do, what to do? Since I have been spending more time on configuring the LimeSDR I revived about the same, I time hadn't even gotten a chance to do more than read the setup instruction and config. the tools for the Zync in Vivado. I' still not sure if I should spring for the Simulink tools for DSP and SDR applications even
  4. Take my advice with a grain of salt. But why would you want to introduce the extra complexity of a RN-42 BT protocol and all that could go wrong with that PMOD set up? if there are no distance requirements between the to FPGAs Dan's idea feels like the best rout.
  5. Thanks, Would you have any idea about when the updated tutorial can be expected? I would love to see a tutorial just about using 3rd party IPs for the Zync/Vivado environment like from OpenCores and the like. Since the Zync device is not a normal FPGA it has been a bit hard to translate tutorials written for the vanilla FPGAs.
  6. jpeyron, Thanks for the reply and link. I have run into more options not discussed in the tutorial can you recommend an appropriate place to post? After generating a bitstream leaving the default options I am asked to choose from: Open Implementation Design view reports open hardware manager generate memory config file
  7. I am walking through the Getting Started With Zynq tutorial and am at a crossroads in the design. In step 5.2) of the tutorial: "After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the Design Sources tab, right-click on the block diagram file. We labeled it “design_1.bd” and select Create HDL Wrapper." Vivado gives me a pop up with two options and the tutorial doesn't provide any guidance. If I were not so new to FPGA design maybe the answer would be clear as day but as a beginner I wish these detail were more clear.
  8. I got the License generated, loaded and installed successfully. Thanks for the link jpeyron !
  9. I was able to get Vivado License Manager to run by uninstalling all 2012 Microsoft C++ Redistrobutable packages then rebooting. Once reboot click on Vivado License Manager... actually I don't know what I did but I got VLM to launch. Now I need to figure out what I need to to after that.
  10. Im unclear if I need to unistall any year or only the 2012 C++ redistrobutable?
  11. Thanks, I don't know why I could't find that forum conversation. I will let you know if it works. It sounds like I need to uninstall all 2012 C++ redist then click the VLM and reinstall the 2012 C++ package (again).
  12. When I click Vivado License Manager to activate the Vivado Design Tools license, I am met with a window asking me to either "repair", or "uninstall" Microsoft 2012 C++ redistrobutables. It doesn't matter if I repair, I get the same message next time. If I uninstall I get the message asking for the installation of the same Microsoft C++ package. If I install it the next time I click on VLM I get the same error. Does anyone know how to work around this problem? Iv included my Xilinx install log. Im sort of new to FPGA development, any help is greatly appreciated. xinstall.log
  13. I am having a hell of a time activating my license. When I click on the Vivado License Manager I get an error: "Error when launching C:\Xilinx\Vivado\2016.4\bin\vlm.bat: Launcher time out " I read something about uninstalling any Microsoft Redistributes Package prior to 2010. Dose anyone know how to work around this problem? I have several but I know if I get rid of them it will crash other programs that put them there. I included my install log. xinstall.log