B SULLY

Members
  • Content Count

    20
  • Joined

  • Last visited

About B SULLY

  • Rank
    Member

Profile Information

  • Gender
    Male
  • Interests
    Love to learn...

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When looking in "C:\Zynq_Book\first_zynq_design\first_zynq_design.sdk\LED_test_bsp\ps7_cortexa9_0\include", there is indeed no "xgpio.h" file. Could this be due to errors I received in the during implementation? Such as: WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [C:/Zynq_Book/first_zynq_design/first_zynq_design.runs/impl_1/.Xil/Vivado22392YogaFlex/dcp_3/first_zynq_system_axi_gpio_0_0.edf:3791] I think the first of which was: "ERROR: [Ipptcl 7-1] Could not find packager TCL script '/scripts/ip/ipx.tcl'" Another was: ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_xilinx_com_ip_processing_system7_5_5': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing"source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_xilinx_com_ip_processing_system7_5_5 ]" and CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'first_zynq_system_processing_system7_0_0'. Error during customization. The list continues (can provide full more tcl messages and logs) but I was able to generate a bitstream. Another aggravating factor could be that I ran into the 2012 Microsoft C/C++ Redistributable compatibility issue when starting the SDK from within the IDE. To solve that problem I renamed xvcdredlist.ext in the "C:\Xilinx\SDK\2016.4\tps\win64" folder and launched from the Start menu. Since most of the errors encountered have to do with input/output and GPIO, I kind of think and hope that the root problem has to do with the following warning thrown in the Vivado 2016.4 IDE / IP Integrator synthesis/ implementation: "WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. " My question is whether all these errors received in the implementation stage are related to the error in the SDK. If that is the case than would solving the following error ( the very first error) solve all? if so how would I go about that? If in your answer you could as much explanation as needed to help me understand how to troubleshoot this myself, it would be most appreciated. As I am new to FPGA development. This is the tcl command that started it all: "create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0" and produced this: couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_design_1_c_addsub_0_0': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing "source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_design_1_c_addsub_0_0 ]" If these warnings and errors are unrelated could I successfully download the bitstream to my Zybo board without fixing the errors encountered while using the IP Integrator and only fixing the fatal error: xgpio.h: No such file or directory in the SDK? If so, is the best way to do that? Finally just to recap my questions are to help me understand the warning/error messages and ultimately resolve the xgpio.h no such file error, and as follows in no particular order: What dose first_zynq_systemj/axi_gpio[0] is not directly connected to top level port mean? As this would help me solve the IOSTANDARD error. Would renaming xvcredlist.exe create problems elsewhere? What is this tcl command trying to achieve and why is giving the error? create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 Why can I see xgpio.h in the project explorer tab under src/LED_test_tut1C.c but not under the C/C++ projects tab? How can I fix the xgpio.h: no such file or Directory in the SDK? Thank you for your attention. I apologize for the wordy post and welcome anyone who can shed light on any of these questions.
  2. I seem to have lost my original Zybo board and am wondering if I purchased a new one, maybe even the Z7 would my existing voucher and Xilinx license work for a new board. I think that is the only think that has survived a recent move, (the voucher and Xilinx Vvado software).
  3. So I have come to the conclusion that My Zych/Zybo dev board has been stolen or misplaced. I am wandering if the "node locked" (OR) "device locked Xilinx Dev packages that I purchased will work I I get a new board of the same make as model. I had the zync 7010. What to do, what to do? Since I have been spending more time on configuring the LimeSDR I revived about the same, I time hadn't even gotten a chance to do more than read the setup instruction and config. the tools for the Zync in Vivado. I' still not sure if I should spring for the Simulink tools for DSP and SDR applications even though I am learning this DSP stuff on my own and the math can be intimidating. Can anyone provide any advice? Is there another product out there that would be better suited to my DSP SDR applications. I also want to build a toxin monitoring system. No clue where to start on that one. Thanks in advance. Brian S.
  4. Take my advice with a grain of salt. But why would you want to introduce the extra complexity of a RN-42 BT protocol and all that could go wrong with that PMOD set up? if there are no distance requirements between the to FPGAs Dan's idea feels like the best rout.
  5. Thanks, Would you have any idea about when the updated tutorial can be expected? I would love to see a tutorial just about using 3rd party IPs for the Zync/Vivado environment like from OpenCores and the like. Since the Zync device is not a normal FPGA it has been a bit hard to translate tutorials written for the vanilla FPGAs.
  6. jpeyron, Thanks for the reply and link. I have run into more options not discussed in the tutorial can you recommend an appropriate place to post? After generating a bitstream leaving the default options I am asked to choose from: Open Implementation Design view reports open hardware manager generate memory config file
  7. I am walking through the Getting Started With Zynq tutorial and am at a crossroads in the design. In step 5.2) of the tutorial: "After the design validation step we will proceed with creating a HDL System Wrapper. In the block design window, under the Design Sources tab, right-click on the block diagram file. We labeled it “design_1.bd” and select Create HDL Wrapper." Vivado gives me a pop up with two options and the tutorial doesn't provide any guidance. If I were not so new to FPGA design maybe the answer would be clear as day but as a beginner I wish these detail were more clear. Copy generated wrapper to allow user edits Let VIvado manage wrapper and auto-update The window also states;"You can either add or copy the HDL wrapper file to the project. Use copy option if you would like to modify this file." The next step moves on to generate a bitstream file so I'm going to assume that this file will not be edited any longer. I wish the tutorial would provide a bit more context to the steps laid out and how the operations used in this simple project would/could be used in another project. So far I appears that once I'm done this this tutorial I will only have learned how to accomplish the same task, only with a bit more confidence. After step 6 I am given another window the tutorial does not make any mention of. The window is titled Launch Runs with text; "Launch the selected synthesis or implementation runs." and provides 3 choices. Launch runs on local host: Generate scrips only Number of jobs [2] {with option to change value} There is also a choice of Launch directory. On this one I'm totally clueless. I realize that Diligent is not responsible for changes in the Vivado IDE but I as a company focused on education I think it could do better on updating tutorials to accurately reflect the changes in Vivado. I would also LOVE to see more Zybo tutorials, they are far and few between on the net. The book is alright but a bit difficult to navigate to topics the relevant for beginners. If anyone could respond with instruction on how I SHOULD have proceed with these options and what any of these options really mean I would appreciate it, as I have now come across some warnings in the TCL console about needing a "AXI BFM license to run".
  8. I got the License generated, loaded and installed successfully. Thanks for the link jpeyron !
  9. I was able to get Vivado License Manager to run by uninstalling all 2012 Microsoft C++ Redistrobutable packages then rebooting. Once reboot click on Vivado License Manager... actually I don't know what I did but I got VLM to launch. Now I need to figure out what I need to to after that.
  10. Im unclear if I need to unistall any year or only the 2012 C++ redistrobutable?
  11. Thanks, I don't know why I could't find that forum conversation. I will let you know if it works. It sounds like I need to uninstall all 2012 C++ redist then click the VLM and reinstall the 2012 C++ package (again).
  12. When I click Vivado License Manager to activate the Vivado Design Tools license, I am met with a window asking me to either "repair", or "uninstall" Microsoft 2012 C++ redistrobutables. It doesn't matter if I repair, I get the same message next time. If I uninstall I get the message asking for the installation of the same Microsoft C++ package. If I install it the next time I click on VLM I get the same error. Does anyone know how to work around this problem? Iv included my Xilinx install log. Im sort of new to FPGA development, any help is greatly appreciated. xinstall.log
  13. I am having a hell of a time activating my license. When I click on the Vivado License Manager I get an error: "Error when launching C:\Xilinx\Vivado\2016.4\bin\vlm.bat: Launcher time out " I read something about uninstalling any Microsoft Redistributes Package prior to 2010. Dose anyone know how to work around this problem? I have several but I know if I get rid of them it will crash other programs that put them there. I included my install log. xinstall.log