armin

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Everything posted by armin

  1. Hi Jon, I use Arty board xc7a35t-1L. and vivado 208.2
  2. Hey, Jon, @jpeyron I used 2016,3 and 2018.2. In the first version the error was due to version, and in the second one it asks for IP updates. I have a problem now and it is the version of XilIsf. it is 5.11 and in tutorial, it has been mentioned it should be at least 5.2. then there is no option to change it how can I handle it? Thanks Armin
  3. By opening the project I have some errors. IIt cannot find the design files
  4. Sorry I didnt get the procedure, I have a UART port on board which I use for programming the FPGA.then in this case, you mean program the FPGA via these 2 ports?(e.g., via a converter?)Please let me know what you mean exaclty
  5. Thanx for reply. I consider the answer as an alternative standard solution.Lets forget for a while bluetooth issue, I am asuming TX RX ports does not work properly. I am wondering whether we can set two other IO pins (except pins that are used for UART port on ARTY board) as TX and RX ? here in my design, I used the following port as TX and RX ports. My uestion is whether these ports really works properly as TX and RX? or extra hardware should be assigned. If they need further hardware module how can I implement it? Thanks Armin
  6. Hey Guys, Im trying to connect HC05 Bluetooth module to my arty board. For this reason, first I implemented a serial module to read data, then I connect an HC05 module to the Arty board via Pmode connectors (Pmod jb connectors): set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports {UART_TX}]; set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports {UART_RX}]; about serial port, I am 00% sure it works properly with baud rate 9600 because I checked it first with a USB port serial communication and it works perfectly. the program is as follow: I send 8-bit data and data value should be shown in bit format on the LED. As I said it works properly via normal USB serial port but it doesn't work with the HC05 module. Does anyone of you have an idea why? here is the VHDL code (as I stated serial interface module works properly with USB port): library ieee; use ieee.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity main is port( CLK : in std_logic; UART_TX : out std_logic; UART_RX : in std_logic; BLUE_LED : out std_logic_vector(3 downto 0); GREEN_LED : out std_logic_vector(3 downto 0); RED_LED : out std_logic_vector(3 downto 0); LED : out std_logic_vector(3 downto 0) ); end entity; architecture behaviour of main is component uart is port (CLK : in std_logic; UART_RXD : in std_logic; UART_DATA_READ : out std_LOGIC_VECTOR(7 downto 0); UART_READ_FLAG : out std_logic; UART_DATA_WRITE : IN STD_LOGIC_VECTOR(7 downto 0); response_is_ready : in std_logic; UART_TXD : out std_logic ); end component; signal clock : std_logic; signal data_send : std_logic_vector(7 downto 0); signal data_receive : std_logic_vector(7 downto 0); signal data_ready_to_send : std_logic; signal data_received : std_logic; signal LED_VALUE : std_logic_vector(3 downto 0); signal UART_RX_S : std_logic:='0'; signal UART_TX_S : std_logic:='0'; signal i_int : integer:=0; type LED_STATUS is (LED_ON,LED_OFF,CHANGE_COLOR,INIT); signal LED_STATE : LED_STATUS := INIT; begin inst_UART:uart port map( CLK => CLK, UART_RXD => UART_RX_S, UART_TXD => UART_TX_S, UART_DATA_READ => DATA_Receive, UART_DATA_WRITE => DATA_Send, response_is_ready => data_ready_to_send ); inst_proc:process(clk,DATA_Receive,LED_STATE) --variable i: integer:=0; begin if(rising_edge(clock)) then GREEN_LED<=DATA_Receive(3 downto 0); LED_VALUE<=DATA_Receive(7 downto 4); end if; end process; CLOCK<=CLK; LED<=LED_VALUE; UART_TX<=UART_TX_S; UART_RX_S<=UART_RX; end architecture; Thx