Notarobot

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Everything posted by Notarobot

  1. Hi @Bilal29 You can find two examples of default XADC usage in Xilinx library Xilinx\SDK\201....\data\embeddedsw\XilinxProcessorIPLib\drivers\xadcps_v2_2\examples It is well documented and it pretty much effortless. Everything is done in SDK, no hardware configuration is required. It worked for me. I don't know what is your goal but these examples could be a good starting point. Good luck!
  2. Notarobot

    Stuck in SDK

    Kris, Printing via xil_print is using STDIO by default and could reconfigured in Vivado and SDK. With little info you provided a lot left for guessing. My last recommendation is to pay attention to a configuration of your build in SDK. The interrupt interrupt service routine (ISR) might not work if GCC compiler has optimization ON. To make it work the variable in the ISR should be declared volatile. Debug build usually has flag -O0 that optimization none. Good luck!
  3. Notarobot

    Stuck in SDK

    Hi, Kris, I noticed uart_rtl line on your diagram and assumed that it was for xil_printf. It is easier to use standard UART connected to MIO which doesn't need PL blocks. I recommend to search Avnet.com or Zedboard.org for Introduction to Zynq Lab 6 called "Adding Interrupts from the Custom PL Peripheral". Also try to set Integrated Logic Analyzer (ILA). It is extremely useful to debigging.
  4. Notarobot

    Stuck in SDK

    Hi Kris, Based on info you provided it could be many different things. For example, why are you using uart_rtl instead of UART1 or UART0? This could be a configurattion issue. Using interrupts for buttons is another tricky part which requires proper configuration not described in your post. I would start with known path and upgrade gradually. In the past I tested the original Zybo with a trivial button-LED project and attached three files related to it. Try it if you want. The project requires Zybo board file and AXI configuration. SDK UART console is used for xil_printf. Goo luck! BTN_LED_c.txt Filter_vhd.txt
  5. Notarobot

    Reading Pmod AD1 value

    Hello wing, In my experience Digilent project here is the most comprehesive use case of PmodAD1 on Zynq boards. It allows for running either continuos and single acquisition on both channels. Also do a search of Digilent forum, you should find block diagrams related to you questions.
  6. Hi EELE First of all I would recommend PmodAD1 for your experimentation. It contains two ADC chips with 12-bit resolution. I've used it successfully with Zybo 7000 for data acquisition at 1MHz sample rate and it worked at 2 MHz as well. Then search the forum on Google using request: site:forum.digilentinc.com/ PmodAD1 You will get a lot of very useful information for making your decisions. I believe this is the shortest path to a knowledge you are looking for.
  7. @Jonathon Kay My recommendation is to start with this board and follow tutorials from here. Download and install recommended Vivado versions not the latest. This board is very affordable and has everything to start. Tutorials will give you a picture of the design process with Vivado. It will help to see integration of the FPGA part in the system. Udemy Zynq tutorials are applicable to this board with minor corrections. I wish to have this when I started. It might be hard but it is a lot of fun as well and without fun who would do it.
  8. @Jonathon Kay You definitely can. Just give it some time. It took me three month in the beginning to program my first working VHDL code. Personally, I recommend VHDL because in my view its structure is a closer reflection of hardware. I agree with zygot that you can learn programming without any board just in Xilinx Vivado. Keep in mind that you will need to learn Vivado and I recommend video tutorials. Udemy.com is not bad for fast learning. However, programming a physical board brings more satisfaction than simulations. Zedboard seems to be an overkill for your goals. I had good experience with less expensive Zybo and, especially, with the MicroZed. The latter is designed with LVDS FPGA I/O thus capable to operate at much higher data rates then the Zybo board. Pretty much everything developed for the Zybo and Zedboard is applicable to the MicroZed. As zygot explained, Zynq is a combination of two very different hardware: ARM cores and FPGA. It complicates using it, however, it also allows to achieve better efficiency and functionality in a smaller package. I am convinced that it is worth the effort to learn. Where to start? I would start with video tutorials explaining Vivado and then would start learning VHDL using the Vivado editor and simulator. Good luck!
  9. EELE, Don't waste your time and buy any board before you understanf what is involved in such development. Since you are newbie you have a lot ahead of you. In my opinion you need the board with LVDS qualified for data rates required by the ADC chip interface. I recommend to look at the boards from Avnet. They are well documented and I had good experience with a couple of their board. You might learn from Red Pitaya project as well. Since time is money I would join zygot recommending appropriate digital scope if this is a one time need. Good Luck!
  10. Hi zygot, I have to agree with you that lack of full schematic irritates, however, it's still possible to utilize it for one time projects. Besides, they provide a partial schematic covering ADC interfaces. Also, it might be possible to accomplish whatever the poster wants by using available software resources. I am not sure that he needs any HW design but configuration. I have this thing (14 bit version) and use it in my work mostly for measurements and as a signal source. Its ADC and DAC are excellent. My point that making custom hardware will triple the cost and development time.
  11. Hi herve, It is not clear what are you expecting to hear. Are you looking for a commercial module with firmware or just an option for your own design? There are a number of ICs from Analog Devices, TI, Maxim that satisfy your sampling rate requirements and resolution, for a example, ADC chips LTC2313, LTC2314. However, they require high frequency (>=40MHz) clock, thus, high frequency connector to the FPGA board. Personally, I think Avnet MicroZed board would be a good base for your design. Another option is to look at evaluation boards from ADC, DAC chip vendors. Typically, they are very good for learning capabilities of the product and recognizing gap we need to fill. Take a look at the Red Pitaya package. It might be overkill but has everything you might need. Good luck!
  12. Arjun, For a standalone mode if you are going to use FatFS file system with Xilinx sdps drivers the limits can be found here Practically 32GB SD card worked perfectly in my experience. Under Linux OS the size could be different depending on version of OS.
  13. Hi, Abdul, Here are my notes/recommendations: 1. Open your block diagram in Vivado where you created BRAM configuration and then check the address editor. You should see whether the BRAM address was assigned. If you find assigned see axi_bram_ctrl_0 OffsetAdress and the Range then the BRAM was created and mapped to the memory. 2. Writing and reading from BRAM requires a clock signal. Check Xilinx templates for BRAM which you can access inside the Vivado. I am not sure that the code you've used to write into BRAM does anything. 3. You don't use an absolute address in your HDL when BRAM created in Vivado. Vivado maps the address 0x4000_0000 to 0. So you can start from the address 0 and it will be the lowest address of the BRAM. If your don't use Vivado then you will need to define your block in HDL and include addresses, and many other parameters. 4. The C-code in SDK should use BRAM address from the file parameters.h. You just need to use XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR as the begining of the BRAM address space. 5. You can treat BRAM as RAM meaning that all read/write operators are the same. For example you can copy BRAM content into the RAM: for(i = 0 ; i < BRAM_SIZE ; i++) *(destination + i) = *(source + i); where source = XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR Disclaimer: always read documentation, whatever you find on Internet might not be correct. Good luck!
  14. In my humble opinion, FSM is the best architecture for the supervisory controller regardless of its implementation. Since the poster indicated AVR (C-code) experience I believe that using Microblaze would be easier or less time consuming because pretty much everything can be accomplished in C-code. However, without knowing the requirements specification this is just my opinion based on personal experience. It should be mentioned that Xilinx provides FSM templates for both VHDL and Verilog. Also, it is imperative to simulate FSM to make sure that it doesn't have dead states. Simulink Stateflow is a good tool for designing FSMs. C-code implementations of FSMs could be found in textbooks.
  15. Dear Abdul, Take a time to describe your project and then you will have better chances to get a useful answer.
  16. I don't believe this is a bug but rather a misunderstanding of VHDL. Unfortunately, VHDL process block is very vaguely described in textbooks. In VHDL statements within the process are carried out sequentially. Moving a statement from one position to another can produce a different outcome. However, it depends on a type of statement, for example, values assigned to signals are not carried out immediately but scheduled to occur at the end of the processor or on clock events. I would recommend to check how it works by simulating a piece of code in doubt.
  17. Notarobot

    CAN Data in PL

    Hi CodeMagics, Let me try to answer your questions. 1. Unless you require extremely low latency the PS can be suitable for real time. You just need to operate it in a standalone (or bare metal) mode. 2. To my knowledge CABbus does not have master-slave relationship between nodes. The user can define such by programming the messages' ID. Otherwise all nodes can send messages at any time. 3. Due to its complexity CAN bus requires substantial code overhead. To my knowledge there is no open source VHDL or Verilog library supporting CAN. However, there are plenty of IP for microcontrollers. Xilinx offers free IP for Zynq PS as well. You can find it in Vivado SDK, for example, in the folder Xilinx\SDK\2018.1\data\embeddedsw\XilinxProcessorIPLib\drivers\canps_v2_1 Since Zynq PS is equipped with two CAN controllers the only thing you would need is a PHY module, for example, SN65HVD230 CAN breakout board. Digilent offers CAN Pmod as well, however, it uses a chip with CAN controller which is redundant in that case. It is however, useful when you need to use FPGA board without the ARM core. I would recommend searching Digilent forums.
  18. The JF connector is physically connected to MIO ports. These ports allows to connect such peripheral as UART and CAN to PS. Configuration of such connections is done in the processing_system7_0 block in Vivado. In my understanding they are not present in the block design because there is no easy way to utilize it with PL. It is always helpful to check the schematic diagram of the board. Hope I've answered your question.
  19. Tom, You can try to build GnuRadio on your board. There is a script that automates building it on ARM processor running Linux. Once I did it on Samsung chromebook running Ubuntu. In my recollections it took 2 to 3 hours for the completion but in the end it was usable. This Cromebook had 2GB of RAM and 4-core processor. I am not sure the it makes sense to build GnuRadio on Zynq 7000 with its limited resources. Also you will probably need to use remote desktop to graphical output.
  20. Hi newkid_old, It is difficult to diagnoze your problem since the diagram is not complete and it is not clear what is the FPGA code. I assume that BRAM is used by both FPGA logic and Microblaze. Anyway, I would make two notes: 1. The signal wea should be either 8-bit or 4-bit depending your your BRAM configuration. 2. If you write to one port and read from the second you don't need to toggle wea or check it when writing. It can be set once only. Both ports A and B are independent. Make sure that in properties you set write_first for port A and read_first for port B. Since you are using Vivado block design no instantiation of BRAM is needed in the HDL code. It is very easy but for the price of very limited configuration options. It works for me though. Highly recommend to create and run workbench BRAM simulation. BTW, Vivado has help with RAM coding examples explaning proper usage.
  21. Hi shahbaz, I can't help you because information you provided is very sketchy. Did the example work for you? Did you follow the file operations sequence of the TestSD example? I suggest to spend some time learning how to work with the FAT file system. It is very simple.
  22. Mahdi, The idea of using mailbox is interesting but I am not sure that it is helping you to speed up data processing. It definitely adds extra overhead latencies which you wanted to reduce. In similar situations I conducted measurements of latencies using XScuTimer Timer; /* Cortex A9 SCU Private Timer Instance */ Xilinx provides examples of its utilization with Vivado. Obtaining accurate profiling information will make clear where is your bottleneck. Using it with Zybo board I've found that writing to micro SD card can be done at speeds over 10 MB/s, 32-bit RAM operations with AXI at about 30 MB/s. It should be noted that writing to SD card is faster in blocks of 32kB and SD card should be formatted with 32kB sectors aligned. Good luck!
  23. Notarobot

    Fpga XADc

    It is very similar to what you would do using any microprocessor, for example Arduino. The difference is in the hardware. I would recommend seaching this forum for relevant posts.
  24. shahbaz, Typically src folder contains C-code written by the person who design the project. It should contain the main function. You can try attached Xilinx test code. It's rudimentary but you can change it to your needs. Also you don't need to copy Xilinx files into src folder, they will be added to your project from the BSP. TestSD.c
  25. Hi shahbaz, If you are Ok using micro SD card adapter embedded in Zybo I would recommend to use it with the driver xsdps provided by Xilinx. Please note that it is connected and intended for use by PS not PL. The driver is located in Vivado library \embeddedsw\XilinxProcessorIPLib\drivers\sdps In Vivado the only thing is needed is enabling SD card in the processing system. Everything else is done in SDK. There you will need to add library xilffs to the BSP. File system and functions are described in here Good luck!