• Content count

  • Joined

  • Last visited

  • Days Won


Notarobot last won the day on April 16

Notarobot had the most liked content!

About Notarobot

  • Rank
    Prolific Poster
  1. @Tickstart From my experience you will be asked questions to verify claims you put on your resume. Expect, for example, to be asked HDL syntacsis, implementation of I2C protocol, digital filters, etc. Expect also several people who might be your coworkers will talk with you to get the feel and to test your skills. Everything depends on what is the company doing. Most of US companies don't train employees, they might pay for their classes but that's about all. If you are lucky and the company eager to higher you then they can give you time for training. Once more from my experience companies hire people who can bring something the company doesn't have. Think about it and decide if you have something to offer, otherwise spend time on learning. During the Internet boom one of my friends after reading a few software tutorials managed to be hired as a software developer. Needless to say he didn't last long and his experience was painful since he didn't have developer skills.
  2. Why is my Process getting triggered with no change to the sensitivity

    Dear @FlyingBlindOnARocketCycle The debouncer has two purposes: 1) to convert async signal into the signal with edges aligned with the clock that is to bring it into a single clock domain. There is no process sensitivity issue in such design. 2) eliminate multiple ON/OFF contact bounces which are typical for mechanical switches. Depending on the switch technology it takes from 10 to 50 ms to reach stable state. In my experience 20-40 ms worked just fine. It's up to you to decide what hdl to use I just noted that it looks like a latch at the first glance. I also try Xilinx templates before making my own because theirs are 100% synthesizable. I think it is a good practice until you get proficiency. Your post and others helped me to reach understanding and even I've never had such issues in my work I know how to avoid them. Thank you and good luck, bye....
  3. Why is my Process getting triggered with no change to the sensitivity

    @FlyingBlindOnARocketCycle Introducing async button signal into the FPGA creates clock domain crossing problem. This is what you had in the first place, another problem is that you didn't make Xilinx synthesizer aware of this making impossible to create timing goals/constraints. Now anything that brings button signal into the main clock domain should solve the problem. It can be debouncer code or the code you proposed to use which is more like a latch. I am not sure you want one-time event. If I get some spare time I will add debouncer to my code, run it and post results. Also in my experience we should pay very serious attention to Vivado warnings and find the way to clear them. Very useful tool for fixing timing constraints is a "Constraints Wizard" located inside the Implementation section. Unfortunately, this part of FPGA design is very poorly described. Update After adding button debouncer everything works as intended. Single 100 Mhz clock is used and no critical or any serious warnings from Vivado. I post VHDL files and the block diagram just in case somebody wants to verify. DBounce.vhd NBT.vhd
  4. Why is my Process getting triggered with no change to the sensitivity

    Having some time on my hands this weekend I decided to run some tests myself and share results with you. In my opinion, coding the VHDL process is covered very loosely by majority of textbooks and tutorials. In my opinion Xilinx UG901 is the most useful and accurate source. Specifically, I would point to pages 191, 192 describing the syntax and components of VHDL process. I believe that it is better/safer to stick to this guide since they wrote the synthesis tool. BTW, it says: " If any signals are missing from the sensitivity list, the synthesis results can differ from the initial design specification. In this case, Vivado synthesis issues a warning message and adds the missing signals to the sensitivity list." For testing I took liberty to reuse published code with several simplifications and adaptations for my Zybo board. I tested three versions of code. The first one is by the book clock counter as Xilinx recommends: ------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity NBT is Port ( clk : in STD_LOGIC; -- 0.201562 MHz btn0 : in STD_LOGIC; led0 : out STD_LOGIC; led1 : out STD_LOGIC; led2 : out STD_LOGIC; led3 : out STD_LOGIC ); end NBT; architecture Behavioral of NBT is signal up_test : unsigned (18 downto 0) := (others => '0'); begin led0 <= btn0; -- Button LED control led1 <= up_test(16); led2 <= up_test(17); led3 <= up_test(18); count_button_process_triggers: process(clk) begin if rising_edge(clk) then -- "clock event" up_test <= up_test +1; end if; end process; end Behavioral; ---------------- This version worked flawlessly, no critical warnings, etc. Version 2 was modified to count pushing the button as shown below: ---------------- count_button_process_triggers: process(btn0) begin if rising_edge(btn0) then -- "clock event" up_test <= up_test +1; end if; end process; ----------------- The version 2 worked as intended, no false counts, but it produced a number of warnings, specifically, in Timing Check Worst Severity warnings: no_clock, unconstraint_internal_endpoints, - no_output_delay. The version 3 was a copy of Hamster's counter where "clock event" was removed: ----------------- count_button_process_triggers: process(btn0) begin up_test <= up_test +1; end process; ----------------- This version failed to create bitstream with 5 errors, including [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition..... I hope this helps to make conclusions. For me it is obvious that time considerations = constraints should be included. It is impossible to create layout without timing constraints. In many cases Xilinx takes care of this behind the scene using clock parameters but if the clock is not defined by the designer the result is a mess.
  5. Pmod external pinout xdc

    Hi @sga I suggest to try connecting push buttons or an encoder to Pmod port. Change set_property PACKAGE_PIN M15 [get_ports {PMOD1_D0_N }]; # "M15.PMOD1_D0_N" to set_property PACKAGE_PIN M15 [get_ports BTN_1]; Of course, button should supply either 0 or 3.3 V when operated. Create external input port BTN_1 and wire it into AXI GPIO. You might need create VHDL module to deal with button bounce and other things like crossing clock domains but for testing this simple circuit will work. There is an example of programming for reading buttons. The encoder input should be very similar.
  6. Pmod external pinout xdc

    Hello @sga Thank you for clarification, now I better understand your position. Digilent did a great job creating their boards' files. It is so convenient and easy. I'd like to do the same on my project as well. I have Zybo and in the past tested several Pmod modules including PmodOLEDrgb and PmpdOLED which takes fewer resources. At this moment I don't have time for further research but I would try to edit Zybo board.xml to match the minized. It seems reasonable. Also I would start with Pmod simpler than PmodOLEDrgb until you get the first one working. Another way would be manually creating external ports for all 25 IO signals coming out of PmodOLEDrgb with matching names and then adding corresponding constraints lines. I am sure you know that you can make connection any of signals on the diagram, for example, pmod_out_pin7_i to the external port.
  7. Pmod external pinout xdc

    Hello @sga I would recommend: 1. Get a schematic diagram of the Pmod you want to use and make a note or create a table of pin <-> signal designation. 2. Open the file MiniZed_Constraints_Rev1_170613.xdc and find PL Pmod #1 section and replace the signal name on every line with the designation corresponding to your selected Pmod, for example set_property PACKAGE_PIN M15 [get_ports {PMOD1_D0_N }]; # "M15.PMOD1_D0_N" to set_property PACKAGE_PIN M15 [get_ports ADC_D0]; (if you want to use Pmod-AD1, there are three more lines for this Pmod) 3. In Vivado create a block diagram and create external ports for Pmod signals, for example, external input port named ADC_D0, etc. These ports should be wired to either Xilinx IP modules or you custom RTL module. Power pins: GND and 3.3V do not require configuration you just need to verify proper connection. Hope I've answered your question, good luck!
  8. Zybo and PmodCAN

    Dear @mbo If you trace Zybo Pmod JF schematic diagram you will find that - pin JF2 (MIO-10 = Rx in) should be connected to CAN Rx on the PHY breakout board SN65HVD230 or similar, - pin JF3 (MIO-11 = Tx out) should be connected to CAN Tx on the PHY breakout board. - pin JF5 and JF6 - GND and 3.3V power. Please, note that the above mentioned breakout board is does not include CAN controller, CAN controller is implemented in ARM on Zynq. I am not sure that you can use Pmod-CAN is such configuration. I don't have time to investigate this. My recommendation is to get USB-CAN dongle and use PC for monitoring the CANetwork. It will help you to debug and configure your nodes and messages.
  9. 32bit data transfer using uartlite

    I had similar issues with UART on Windows as well. In one case Zynq board was sending large files containing 32bit binary data over UART to PC. When I used SDK terminal I didn't have any glitches but when I used any of Windows terminal applications a few bytes were missing at some points. BTW, binary data itself can be transferred over RS232 you just need an application accepting binary not just text data. In the past I also had similar problems transferring large chunks of data on Windows in Java application. In our findings the issue was related to the serial port buffer overflow. On my projects I use RS232 only for short messaging, data transfer function is delegated to a faster and more reliable CANbus. It took some time to learn how to use CAN but was worth it.
  10. "Breadboardable" 7 series FPGA with lots of lots of GPIOs

    In my opinion cost and demand for a product are deciding factors. Manufacturers don't want to loose money on something that sits in the warehouse. I am sure they do market research before commiting money for development and production which could be substantial. The point is if it's not on the market it's not profitable. It should be noted that affordable price can be achieve only in high volume (>10k). From my experience I would suggest to look at Avnet Microzed with the prototyping carrier card. The carrier card has 200 traces wired from Zynq and you can solder 2 headers for using it on a breadboard. It is up to you to use ARM or just PL. Good Luck!
  11. Zybo and PmodCAN

    @zygot Initially, I tried CAN as a replacement for RS485 which is not supported on Zynq, and found that it's not difficult to implement. I think I showed the way, relevant C-code anyone can find in Xilinx library embeddedsw\XilinxProcessorIPLib\drivers\canps\ . My response to this post was motivated by troubles understanding the way @mbo tried to implement CAN on Zybo. I think it's very awkward approach and I am not sure that it can be successfully accomplished. I hope to spare him from unnecessary suffering.
  12. Zybo and PmodCAN

    @zygot Thank for the advice, I did check the schematic when implemented CAN on Zynq and configuring CAN on MIO 10,11 for using Zybo port JF. You are correct, a PHY = CAN_breakout_board is needed for implementing differential signaling. This is the only purpose of PHY in this particular case. Anyway it was done a while ago and CAN delivered expected results. CAN is fast, low latency communication allowing to put many devices on the same pair of wires. I can add or remove any one without disrupting the network.
  13. Zybo and PmodCAN

    Hi @zygot Yes, it requires MIO to be configured, for example, like this On Zybo these MIO are wired to Pmod JF. You are also correct that PHY = breakout board is needed to implement differential signaling. I've done this on Zybo and on other Zynq board and happy with results. CAN is more complicated but worth the effort. It is fast, reliable, only two wires, and you can put 64 devices on these two wires and since there is no master node you can add/remove any device easily.
  14. Zybo and PmodCAN

    Hello @mbo I am not sure that you are aware that ARM processors on Zynq have two CAN 2.A (2.0B) controllers embedded on the chip. Unless some specific requirements, logic of adding an external controller Pmod-CAN is difficult understand. Pmod-CAN is well suited for boards without Zynq (ARM) capabilities. The only piece of hardware needed to make ARM CAN to work over a pair of twisted wires is a breakout board, for example, like this connected to the Zybo Pmod port JF. This breakout board is required to implement physical CAN interface. You can find JF port configuration searching FPGA forum, check Xilinx provided examples of the driver and you are good to go. You can start with the Xilinx source code but change loopback mode to normal in the configuration call. I would also recommend to have include PC in the network for debugging purposes. For the intreface I would recommend USB-CAN adapter from this open source project. It works with open source software so that you can start with very low monetary investment into your project. Good luck!
  15. Compatibility Pmod Boards <-> Pmod Ports

    @Geralt In my experience differential IO could be a problem if used as single ended. Since these traces are tighly coupled it is expected that when driven independently transients on one trace will create some level of sprious transients on the adjacent trace. Considering this scenario, the ADC counter will count these spikes as coming from the ADC chip producing erroneous result. The only practical mitigation I found working is to control the slope of SPI signals in the xdc constraints file. The other option is to use a different COTS board with shorter traces.