Notarobot

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Notarobot last won the day on October 16

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About Notarobot

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  1. Advice for workstation configuration

    Hello to all, Let me share with you my perspective and you decide which setup suits you. My designs include both HDL, SPICE simulations using vendors tools from TI, Linear Technology and Analog Devices, Matlab and Altium design tools. As much I as would want to get away from Windows, it is the only OS fully supported by majority of vendors. Besides the only opportunity to use full CPU resources and 16GB of RAM is Windows. Virtual machines would degrade performance. Doing designs with many opened desktop windows requires utilization of full capability of 4K primary display and the second 4K monitor. I can't achieve comparable performance with remote desktop. I've done this in the past and try to avoid unless no other way available. My setup consists of high end 4K laptop and 4K monitor. I find it very productive, comfortable, quiet and fast. Since I need to have access to development boards for testing designs I keep everything in one lab space. More powerful desktop processor might save some time during synthesis and optimization but it will add extra time on maintenance of additional computer hardware. My cost/benefit analysis definitely not in favor of remote desktop setup. Simple is good. In my opinion remote setup has merits when sharing and to get away from the fan noise. Hope this helps...
  2. How to get sufficient expertise for planning purposes

    @Jamie I think your approach to use consultants is prudent. You need to buy expert knowledge, otherwise you will waste a lot of time=money. FPGA are popular but few people realise how much know-how is behind its power. I would advise you: 1) Try to do the concept design very carefully with as much details as you can; hire somebody to do this design; 2) Don't try to save money on hardware; buy the most advanced board but the one that is well supported. Hardware is way cheaper that development time. 3) Use Zynq - ARM processors will save you time on supervisory functions, communications, testing, monitoring and health management. I don't know what is your time budget but be aware that without proper FPGA experts your schedule can slide far beyond your estimates. Also look for relevant IP that you can buy. It will save you a lot of time. Digilent is a great resource for education and you might be lucky to find an expert here. As for a professiona / industriall COTS hardware I would suggest also to look on Avnet. I don't know what kind of processing you have in mind but there are very powerful boards available of the shelf. Good luck!
  3. Zybo I2C

    @david.600, In my undestanding there are two ways to implement I2c on Zybo: - using I2C peripherals embedded in ARM; these can be conigured to be connected to Pmod JF because MIO pins can be wired to this Pmod only. You can use MIO configuration and select MIO 10 (scl) and MIO 11 (sda), for example. - using Xilinx AXI_IIC. You can get HDL source code from the PmodRTCC project and modify it to your requirements. Advantage of the first option is that all programming is done in C-code. I am not sure that you can implement interrupts. The second option has fewer limitations. It is possible to use four Pmod ports and implement interrupts but at cost of more coding and FPGA fabric. I think that it might be also slower that ARM peripheral because AXI peripherals introduce latency.
  4. Zybo I2C

    Hi, @david.600 My advice would be to look at the Digilent PmodRTCC. It communicates with the Zynq ARM via I2c. I tested it in the past and it worked as advertised. Communication works two-way. I was able to read RTCC and write settings. Looking at the code provided on GiHub you will find answers for your questions. I made only few modifications when used it because had other components in the system. You can use other devices instead of RTCC, even several devices on the same I2c bus provided they have different addresses. Also I2c is very well supported on Arduino although not very fast. Good luck!
  5. PMODOLEDrgb and SP601

    Hello Oliver, First of all I need to say that am not a member of Digilent and please excuse me for offering my perspective. You definitely can find VHDL code to implement SPI. Most likely you can find appropriate implementation code for a processor core. Since the SP601 board is not supported by Vivado will need to spend a sizable amount of time gluing all code together. Depending on your VHDL and hardware experience it might take from 2 days to 15 days to make it work. If you put a value on you time it would be more efficient to procure modern Zynq board and utilize Digilent and Xilinx IP. Using Vivado it takes only few hours to put together project with PmodOLEDgrd. No only you would free your time for more demanding projects but also significantly expand hardware / software capabilities. The cost of mass produced hardware is low compare with the cost of labor. The cost of good quality Digilent or Avnet Zynq boards is less than one day salary of an electronic engineer. Good luck!
  6. No serial port when connecting to shared JTAG/UART USB

    @clara.daia From my personal experience Linux requires a number of configuration tweaks for making Vivado functional. It might help to review attached summary of tweaks for Ubuntu 16 implemented when I installed Vivado 2016.4. It works for me. Don't take it verbatim, use what's necessary. You can save time using proven/supported Linux distro on a virtual machine if your version is missing something. Linux_fixes.txt
  7. Using Canbus on the Zynq 7000 board

    @david.600 There are two Xilinx documents describing ARM implememtation of CAN interface controller: UG585 and PG096. CAN protocol is much more elaborate than RS232 or RS485 and I am not sure that starting oroginal development of CAN controller has reasonable justification. PmodCAN is an option but it will duplicate functionality of the existing controller implemented in Zynq. In my personal opinion the easiest way to implement CAN would be using approach described in UG585. You will need to use CAN SN65HVD230 breakout board, connect it to JF MIO Pmod and configure Zynq processing system for CAN0, for example. Xilinx also provides canps driver, example and test application in Vivado XilinxProcessorIPLib. Good luck!
  8. Hi Jon,

    Would it be possible to share with me JTAG over USB schematic diagram used on Zybo board?

    On my custom card I want to combine UART and JTAG on a single USB connector. Digilent JTAG over UART-USB is very reliable and works seemlessly.

    Thank you.

    1. jpeyron

      jpeyron

      Hi @Notarobot,

      You will need to e-mail support.digilent@ni.com to discuss getting this information.

      cheers,

      Jon

    2. Notarobot

      Notarobot

      Thank you.

    3. jpeyron

      jpeyron

      Hi @Notarobot,

      Not a problem.

      cheers,

      Jon

  9. FPGA based PWM generation

    @JColvin Excellent move, this can be a place where we can share lucky findings and discuss engineering choices. Constructive critisism is crucial in technical discussions, it is a feedback that keeps us on the desired trajectory.
  10. Pmods AD1 and DA2 use with ZEDBOARD

    The Pmod AD1 contains two ADC chips thus it is capable to digitize two analog voltages at the same rate simulteneously.
  11. Conflicting two Pmods

    Jon, After trying the suggested update and various hardware configurations I exchausted all reasonable options and changed the target language from VHDL to Verilog. Miraculously, this change produced the desired effect. Now the project works although in a different configuration but this is not important. I am not sure that this is the primary cause of the issue and will continue testing. Thank you for clues and your very valuable support! Have a great day!
  12. Conflicting two Pmods

    Jon, There are no warnings at all. xil_printf doesn't help because the system hangs on the instruction: RTCC_begin(&myDevice, XPAR_PMODRTCC_0_AXI_LITE_IIC_BASEADDR, 0x6F); Debug shows zeros (I have captured once). When I bypass RTCC instructions the second Pmod (AD1) completes its task as designed. I will prepare the project for sharing with you. Thank you!
  13. missing include files xgpio.h

    Hi, In my experience Vivado and SDK are closely following date and time of the files in the project. All files should be in sync, otherwise, SDK doesn't see them. Usually I do click "Refresh" on the tree containg the missing file. The most efficient way is to start SDK from the Vivado after exporting hardware to SDK. In my opinion this is all about syncing files. Hope this will help!
  14. Conflicting two Pmods

    Hello to all, I am looking for help resolving a conflict between two Pmods. The Zybo board is configured in standalone (bare metal) mode. Each of Pmods was tested and worked perfectly well when running alone. It should be noted that RTCC module works also with the Pmod OLED without any issues. However, when I add PmodRTCC to the system it hangs. Debugging indicated that is does have address but no pointer to the myDevice struct. Attached is a block diagram of the system. I am sure that I missed something and hoping that people will spot it quickly. Thank you!
  15. missing Zybo SD card definition

    Hi, Hamster This was confusing for me. Thank you for clarification. I'd like to use PmodSD IP on embedded microSD card instead on Pmod connector. At this time just for prototyping. Initial intent was to define MIO41-47 pins the same way as Pmod, let say JB connector exposing SD for the diagramming. This would allow for very simple intergration the PmodSD IP into the system diagram and etc. However at this moment I can't find clear solution which does not involve manual rewriting configuration files. Hope to hear suggestions from experts with experience. I am very new to Vivado and Zynq. My past experience was mostly pure VHDL projects in ISE and on Actel FPGA with absolutely different software tools. Thank you for reading and ANY SUGGESTIONS! Update: I just discovered that Xilinx included support for SD cards into SDK and no HDL code is needed for using microSD card on Zybo only enabling the SD0 on MIO 41-45. Under these circumstances using PmodSD code does not make sense, thus, any further effort in this direction. Thank you all for reading and response!