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  1. Dear @Tickstart I am afraid you are getting confused with multiple points of view. Let me add one more. FPGAs are used as event driven machines. They produce output based on combination of inputs and these outputs change when there is change on input(s). It can be completely asynchronous machine if you don't need time stimulus. Then there is no need for clock. If your design have regular repetitive event then a clock is your help. Clocks a needed also for generating of signals, communication, and implementing delays. In VHDL many processes have clock in a list of stimuli but it depends on its purpose. It is necessary for synchronization only. Events in many control systems are random and the beauty of FPGA that they can respond almost immediately as oppose to clocked processor based controller. The latest industrial PLCs are constructed on FPGAs to achieve fast and deterministic response. Good luck! P.S. It should be mentioned that VHDL has operators for simulation only. They are not synthesizable, for example "wait". Clock driven counter is used instead for the implementation.
  2. mysql

    @JovanYong In professional world such data collection system is called SCADA that is the "Supervisory Control and Data Acqusition". I have substantial experience with commercial systems and I would love to have similar for environmental data. However, commercial is way too expensive for hobby and as everything requires training. I would suggest to research open source SCADA systems before diving into coding. BTW, MySQL workbench is just a management utility. I am not aware of using it as a data bridge. I also assume that you aware extracting data from the database requires customized software. For a small number of parameters like yours you don't really need relational database, you can accomplish your task using single 2d table.
  3. Zynq combination of processors and FPGA increases productivity substantially. If you didn't use new SDK be patient and it's worth it.
  4. Were you able to run successfully C code for the XADC? This case was covered on this forum here This test would allow to rule out most of possible configuration mistakes. Personally, I can't help you with Verilog, I am not profficient.
  5. @hamster, Using this occasion I wanted to thank you for you contributions. I've found a lot to learn from your site as well as from posts on this forum. The debouncer code I posted is not mine. It is very similar to yours and I chose it because it has pretty clear description. Also in my practice I use testbenches whenever I can. In cases when FPGA controls the equipment trial and error approach would be very costly. When the testbench is too complicated we used to built a physical test setup. Exhaustive testing is the major prerequisite of success in commercial environment.
  6. Having spare time on hands and following the last post I took a liberty to create a testbench using published materials. The VHDL code was taken from here and the template for the testbench was created using this online tool here The testbench is for the debouncer only and it's very simplistic but sufficient as a starting point. It is easy to copy internal signals to the entity port and get insights into its internal behaviour. Thanks! TB_Debouncer.vhd DBounce.vhd
  7. I agree, sorry for that.
  8. It seems that FPGA became fashionable once more. It motivates but not enough. In my opinion in order to learn HDL one should have real need to use FPGAs. In my case I simply didn't have any other viable technical solution. It should be noted that complexity can quickly get at an unmanageable level. For this reason I appreciate very much introduction by Xilinx of IP integrator with block design. It creates upper level of abstraction and automate interfacing. I believe that it follows the industry trends along with Mathworks and others.
  9. Learning curve of HDL design is very steep especially for people without background in digital circuits. The fact that every statement outside a process is concurrent makes it very difficult to control/predict behavior. Plus it is difficult to predict how design decisions will affect compliance with the time constraints. Plus many other factors which one can learn only from making these decisions. I tend to believe that the best way to learn is on other people examples. That is one of the major values of this forum. Some posters on this forum don’t care to explain what the issue they need to help with, but simply want complete solution. I admire D@n, Hamster and Digilent personnel to have patience for this. I am glad that Tickstart made an effort to explain his project. Thank you, zygot for raising important questions. Have a good weekend.
  10. Hi, here is a good explanation and code for the debouncer. Cheers!
  11. arduino uno

    It is possible to put Arduino to sleep that is very low power consumption mode for a period of time. Periodicity of this mode is determined by the Watchdog timer. When waken the Arduino will check communication and do whatever it is programmed to do and then go to sleep. If you make very low duty cycle the average consumption will be also very low. In my recollection not all processors have such capability. You will need to check the datasheet. All information for this kind of use case is available on Internet.
  12. Typically Teraterm terminal app worked for me under Windows.
  13. Can you build OpenSSL from the source?
  14. To all, I wanted to add a few notes to this discussion. High complexity of modern control systems can be dealt with by extensive modeling and optimization on the design stage. Simulink has tools to deal with this. It was the main tool in several of my projects all the way from proposal stage to the design and implementation. FYI, all car computers were designed with it. A car computer code is mostly a bunch of nested state machines and PID controllers. All of it can be tested automatically before going into hardware production. They also generate code automatically and the beauty of this that it works and bugs free. Personally I generated only C-code from the custom Simulink motor control model. The code was readable, although name were cryptic, which we changed. By the way it is always difficult to read code written by somebody else, but everyone should be able to understand block diagrams. As with every new tool one should choose wisely because it requires investment in $$ and time (which is also $$). Learning curve is steep. Modeling is as good as the model you created. It can easily produce a lot of good looking but false results. Custom system will also need to create custom libraries. However, in my opinion it is indispensable in the system design. It should be noted that the license is perpetual but requires annual subscription fee to obtain updates. It is optional. Looking at the rising complexity of the systems and expectations to produce at lower cost / shorter time I don't see other way but to use automatic code generation. Also when we face deadlines the HDL development can be very stressful and I appreciate any tool that help me to reduce it. Hope it makes sense.
  15. Hi Paul, 1. The block RAM picture was conceptial. More details are in the picture. GPIOs are on the left. 2. You can create the new port on the block diagram by clicking right mouse button (or Ctrl+K) and then defining its direction, etc. 3. Constraints file in Vivado has .xdc extention. Digilent supplies definition .xdc for their boards which makes life easier.