Notarobot

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Notarobot last won the day on November 16 2017

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  1. Using Canbus on the Zynq 7000 board

    @david.600, Thank you for your answer. To my knowledge J1939 requires 29 bit Identifier. Hope you set this the same on both sides. It was one of my problems initially. My advice to test loopback, it will rule out a number of possible issues.
  2. Using Canbus on the Zynq 7000 board

    Hi @david.600 I am wondering what are you using for communication with the PmodCAN/Zynq, specifically, hardware and software. In my experience I've spent a some of time making sure PC side of CAN is working properly.
  3. Interfaceing FPGA and an external chip and timing constraints

    Hi @chuchang In my humble opinion contraints on your 100 MHz clock are too relaxed. I would keep delay within 0.2 ns. Also, I would put constraints on the output data lines delay, especially if you are sending parallel data. The same should be done on the data coming from your external source. Hope you find this useful, good luck!
  4. @emfries I am not familiar with Cmod7, however, you may try my checklist I used on Zybo board. The project name is Zybo_example and SDK app is called Hello. Programming Zybo using QSPI Flash 1. Create a base zynq design and verify. 2. Generate the top wrapper from the block design and don't let vivado auto update the wrapper. 1. Bitstream Settings -> check [bin_file ]. 2. Configure additional bitstream settings highlighted in blue at the top of the window. On the following window change the property Enable Bitstream Compresssion to TRUE then select OK until both windows are closed. 3. Generate bitstream 4. File -> export -> hardware (include bitstream) 5. Open sdk 3. File-> new -> application project, create new name 4. Select FSBL and create FSBL project 5. Update the BSP to use the updated version of xilisf. To do this, right click on the BSP and select Board Support Package settings and make sure that xilisf is checked 6. Xilinx tools-> create boot image a. Choose .bif file output location inside work directory b. Partition type: bootloader add <FSBL>.elf -> \\UserX\Zybo_example\Zybo_example.sdk\Hello\Debug\Hello.elf c. Partition type: datafile add hardware .bit file -> \\UserX\Zybo_example\Zybo_example.sdk\design_1_wrapper_hw_platform_0\design_1_wrapper.bit d. Partition type: datafile add SDK C-application .elf file -> \\UserX\Zybo_example\Zybo_example.sdk\Hello\Debug\Hello.elf 7. Click create image 8. SDK Xilinx tools -> program flash and choose created .bin file 9. Switch jumper from JTAG to QSPI 10. Cycle power to boot from QSPI Good luck!
  5. Hi @techno-rogue I might be wrong but it appears from the picture that the Pmod output is directly connected to 50 Ohms coax cable. The scope is showing about 2V amplitude which is inconsistent with the description of the experiment but consistent with the driving 50 Ohms directly from logic. Note that Zybo traces probably designed to have 60 Ohms impedance. Tail waves on the waveforms indicate impedance mismatch between 50 Ohms load and driving impedance. If I would do such experiment I would interface Pmod using high speed line buffer and measure timing on its output. This is how design should be done and this way we would get realistic measurements. Overall I think this is a good learning experience of electronic design theory in practice. Good luck!
  6. @techno-rogue I would suggest 1) check your scope measurements capability here 2) try to add a clock buffer at the Pmod output. Xilinx recommends to us such buffers for clocks. In VHDL it is component BUFG port ( I : in STD_LOGIC; O : out STD_LOGIC); end component;
  7. Dear @techno-rogue It is not clear what is your goal. Do you want to use Zybo as a signal source for some 50 Ohm load or it will interface some kind of digital logic? If the goal is the first one then your experiment can be representitive. However you need to account for the capacitance of the 50 Ohm cable and the bandwidth of the scope you are using. Typically measurements of ns pulse are done using special scope hih impedance probes with very small input capacitance. If your load is some digital logic then the experiment is not representitive because most of 3.3V logic is CMOS and its input is pure capacitance with some loss component. In my experience I was able to drive 40 MHz clock to my custom logic out of Zybo Pmod. I didn't try higher since it was no need. Higher rates can be achived using LVDS but Zybo is not equipped for this. Hope you find it useful.
  8. AXI UARTLITE Data Output

    Glenn, Several sample applications using PS implementation of UART are included with Vivado in data\embeddedsw\XilinxProcessorIPLib\drivers\uartps\ You will learn more from the samples provided by Xilinx. For example, you can see how to utilize interrupts. My application is specific to my project and limited in scope.
  9. AXI UARTLITE Data Output

    @gcp If you are using SDK under Windows OS be aware the it uses little endian which means the bytes will be swapped. This might create some confusion. Also you can use UART0 by connecting PmodRS232 directly to MIO-10, MIO-11 with only one configuration: MIO Configuration -> I/O Peripherals -> select UART0 MIO 10-11. Then, if you want to use UART0 as STDIO, change the STDIO configuration of the BSP from UART1 to UART0: application’s bsp -> Board Support Package Settings -> standalone -> select value ps7_uart_0 for both stdin and stdout On Zybo the PmodRS232 connection looks like shown on the picture. Unfortunately, I don't have time for analysis. Good luck! .
  10. Zybo 7010 Board File Integration

    @Allan Your problem could be resolved very quickly if you care to provide details about what have you tried. I suggest go through "Hello World" project and make sure that USB uart is working.
  11. uart receiving module for 16 or more bits

    @cristian_zanetti Let me suggest CAN interface. Typically, CAN includes 8 bytes data frame and 1Mbits speed. Digilent recently released PmodCAN with the CAN controller. You will need USB-CAN adapter/controller for your PC and, perhaps, proper Matlab instrumentation. Just a suggestion.
  12. Advice for workstation configuration

    Hello to all, Let me share with you my perspective and you decide which setup suits you. My designs include both HDL, SPICE simulations using vendors tools from TI, Linear Technology and Analog Devices, Matlab and Altium design tools. As much I as would want to get away from Windows, it is the only OS fully supported by majority of vendors. Besides the only opportunity to use full CPU resources and 16GB of RAM is Windows. Virtual machines would degrade performance. Doing designs with many opened desktop windows requires utilization of full capability of 4K primary display and the second 4K monitor. I can't achieve comparable performance with remote desktop. I've done this in the past and try to avoid unless no other way available. My setup consists of high end 4K laptop and 4K monitor. I find it very productive, comfortable, quiet and fast. Since I need to have access to development boards for testing designs I keep everything in one lab space. More powerful desktop processor might save some time during synthesis and optimization but it will add extra time on maintenance of additional computer hardware. My cost/benefit analysis definitely not in favor of remote desktop setup. Simple is good. In my opinion remote setup has merits when sharing and to get away from the fan noise. Hope this helps...
  13. How to get sufficient expertise for planning purposes

    @Jamie I think your approach to use consultants is prudent. You need to buy expert knowledge, otherwise you will waste a lot of time=money. FPGA are popular but few people realise how much know-how is behind its power. I would advise you: 1) Try to do the concept design very carefully with as much details as you can; hire somebody to do this design; 2) Don't try to save money on hardware; buy the most advanced board but the one that is well supported. Hardware is way cheaper that development time. 3) Use Zynq - ARM processors will save you time on supervisory functions, communications, testing, monitoring and health management. I don't know what is your time budget but be aware that without proper FPGA experts your schedule can slide far beyond your estimates. Also look for relevant IP that you can buy. It will save you a lot of time. Digilent is a great resource for education and you might be lucky to find an expert here. As for a professiona / industriall COTS hardware I would suggest also to look on Avnet. I don't know what kind of processing you have in mind but there are very powerful boards available of the shelf. Good luck!
  14. Zybo I2C

    @david.600, In my undestanding there are two ways to implement I2c on Zybo: - using I2C peripherals embedded in ARM; these can be conigured to be connected to Pmod JF because MIO pins can be wired to this Pmod only. You can use MIO configuration and select MIO 10 (scl) and MIO 11 (sda), for example. - using Xilinx AXI_IIC. You can get HDL source code from the PmodRTCC project and modify it to your requirements. Advantage of the first option is that all programming is done in C-code. I am not sure that you can implement interrupts. The second option has fewer limitations. It is possible to use four Pmod ports and implement interrupts but at cost of more coding and FPGA fabric. I think that it might be also slower that ARM peripheral because AXI peripherals introduce latency.
  15. Zybo I2C

    Hi, @david.600 My advice would be to look at the Digilent PmodRTCC. It communicates with the Zynq ARM via I2c. I tested it in the past and it worked as advertised. Communication works two-way. I was able to read RTCC and write settings. Looking at the code provided on GiHub you will find answers for your questions. I made only few modifications when used it because had other components in the system. You can use other devices instead of RTCC, even several devices on the same I2c bus provided they have different addresses. Also I2c is very well supported on Arduino although not very fast. Good luck!