Notarobot

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Notarobot last won the day on June 12

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  1. @riche The post you refering to has links to information and even actual project demoing PmodAd1. The Digilent github version makes possible to use only one A/D converter chip while the board is capable to run two ADC in parallel. However, the post included a link to a different version which runs two. In order to run ADC chip you should send to Pmod the chip select signal - CS to start the conversion and a clock signal - SCLK. It takes about 20 clock cycles to complete the conversion. So for 1 MHz conversion rate you would need CS at 1 MHz and SCLK at 20 MHz. However, PL code typically has internal counter = frequency divider which is used to control state machine. In result the input frequency is higher. There are several versions of HDL code for Pmod-AD1: Analog Devices (verilog), Digilent - 2 versions (VHDL) and Hamster (VHDL). By changing the clock frequency you can control the AD conversion rate. I am not aware of detailed description of the demo. I assume that user should read the datasheets for AD7476 and try to understand available code. Good luck!
  2. Hi @mihai5 It is not clear what period of time do you want to measure. For short periods I had used ARM private timer described in the Lab 6 of Avnet training materials It does not need configuration in Vivado. For measurements long period of time with 1 sec accuracy I used Pmod RTCC - real time clock. It was easy to add to the project. The only problem I had was synchonization of time with the computer. This procedure requires a special application passing network time to the RTCC registers. Good luck!
  3. Let me add a few posibilities to the D@n's post. 1. It is possible to create BRAM with the data width up to 1024 bits. This would let you to write 128 bytes simultaneously. In my experience I used 128 bit wide (16 bytes) and 4096 deep. Also you can find Xilinx HDL templates for BRAM inside the Vivado HDL editor by clicking on the light bulb icon. 2. It is possible to accomplish the same goal by using bit arrays, let say 80 bit long. It seems to be simpler because it requires less HDL code but the choice depends on the architecture of your project.
  4. Dear @mihai5 By asking for giving you full IP for your school project you put Digilent staff in a diificult position because it would be unethical to supply you with the complete solution. You had been given sufficient information to finish it. It does require minimal effort to get it working. Please understand this. Good luck!
  5. @mihai5 In my personal opinion one month seems to be very unadequite. I think that just going from the vague concept to development of requirements and testing might take one month. There are a lot of design choices you need to make and learn how to implement them. Perhaps, you can try to use HLS and simulate the concept. Good luck!
  6. @mihai5 It is impossible to make a reasonable advice based on very little information you provided. The decision to go should be based on constraints/ resources of the project, including, how much time to you have for developing this project, is it a production or an educational project, how big is the signature database, what is the TCP/IP data rate, how much time should signature identification take to make the device usable, what is expected gain in performance, etc.
  7. @hamster Thank you for work putting this all together. Only one note. All a-d points are valid but unavoidable. There is no way to avoid time races. Every bus has this issue. The key is to keep these issues under control using timing constraints. Luckily, Xilinx does a good job checking various paths and warning about bad conditions. The same of course is true with other manufacturers.
  8. @Sam Bergami Ealier this year it was a discussion about external XADC use on this forum. Although it was for Zybo board it is still relevant. You will need external mux only if you want to get more channels than available in the XADC that is two. Good luck!
  9. Thank you D@n, I always find something useful for me. Currently, I am using FFT for analysis will definitely benefit from lowering spirious products. But too many things on the plate...
  10. I have to add that recently I had to pay special attention to custom timing constraints on my project. This was a key factor for achieving 1) stable performance and 2) comfortable level of confidence. Unfortunately, it rarely discussed on this forum.
  11. D@n Thank you for your nice and useful tease. Based on the plot one can figure out that it is time-varying estimation. I will try this later. Do you have any practical use of Wavelets in area other than video compression?
  12. @artvvb and @Alex Could you, please, for my education explain why is it bad to drive logic without a clock. I can agree that when you have two periodic signals a synchonizer is a must. However, this case is of combinational logic driven by pretty much random event. I don't see compelling reason to for adding a clock. Perhaps, one practical reason for a clock is for the debouncer. Push buttons without debouncer are hardly usable with FPGAs. I can also see that Xilinx router might have troubles to set timing constraints. Routing error indicates that this might be the problem. Thank you
  13. Hi Sam, May I suggest to elaborate what is it you want to make. It will help others to help you. Based on my knowledge there are at least two type of constrains, one describing physical interface that is binding of the internal logic to the chip pins and the second is about timing constraints. I assume that you are asking about the first one. I am not aware of any possibility to generate such constraints automatically because it is highly dependent on PCB routing which is different for every board. Typically this is decided by the board designer during optimization process. For every commercial board manufacturers include .xdc file describing all connections to installed ports: Pmods, RS232, etc. Since you are using Zedboard you can uncomment statements in .xdc file and rewire some of default connections, for example if you want to use XADC for reading expernal voltages. Xilinx DocNav is the place to learn about constraints. In my experience it is not the easiest but this is information from the first hands without distortions. Good luck!
  14. Dear @Tickstart I might be too late to bring this but hope not. 1. It is typical to use switch - case construct for designing finite state machines. Xilinx even included synthesizable language templates. When you are in the VHDL design window you can see it the Vivado help (click light bulb icon), see the snapshot of it. Using flip-flop seems to be the hardest way to me, however, it is a matter of choice. 2. There is a Digilent project called Active Power Meter reference design with an example of SPI using FSM posted here I would suggest to simulate it for better understanding. Good luck!
  15. @anuar, First of all you need to understand that Vivado is a tool which primary focus is configuring the chip hardware, both the ARM that is PS and the FPGA which is PL. This might require HDL programming but not always. In the case of the DMA example I believe HDL programming is not necessary. Vivado generates important hardware definition files, for example xparameters.h, for the EDK. The main purpose of the EDK is programming of processors either ARM or Microblaze if they are included in the project. Anyway, Vivado and EDK are complmentary and should be used together in sequence. The 2017.1 version works fine for me so far in manual mode. TCL scripts are typically written for the specific Vivado version and quit if the version does not match. You can try to edit the version in the script but it might not work. When starting EDK from Vivado give it some time to load all libraries and .h files generated in the Vivado otherwise you might see error messages and warnings in the C-code. I also recommend to watch training videos and read Xilinx tutorials. It will save you from a great deal of frustration. Good luck!