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About tonyfr

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  1. @[email protected] Thank you very much for you help. i will read the code example on the Github first. And try to use the Gige chip. Thank you very much. tonyfr
  2. @[email protected] yes, i have struggled in this problem for some days. and i have do my best to solve it, but not work. about the Gige chip, maybe it is a good way, but i need to finish the application on PC by myself, and i am not good at it, maybe it need some time. Thank you for you advice, maybe i need to try the Gige chip. tonyfr
  3. @[email protected] Hi, i am new to FPGA-PC communication. i need to transfer the image data from PC to FPGA frame by frame, and receive one frame data, then process the data, then send back the result to the PC, then receive the next frame data. I have tried to use UART port to transfer at 115200 baud from FPGA to PC. Because i need to check the receiving data and change the state between receive/send data state, need some handshake signal, i think UART is not a good choice.
  4. @[email protected] hi, no different work, just large data need to transfer, and UART port is slow. Maybe i need to check my VHDL code and my timing constrain file.
  5. @[email protected] hello, thank you for replay. I know the schematic page missing I just want to transfer data between PC and FPGA, and as describe on the NEXYS VEDIO datasheet, the PC-FPGA Data Transfer (DPTI / DSPI) is micro-usb (J12) and the chip is FT2232h, i just wonder why i can not transfer data as describe signal and timing in the datasheet.
  6. Hello all, I have a problem with the nexys vedio board FT2332h chip programming trying to use the FIFO synchronous Mode. i need to transfer data from PC to FPGA with FT_write(), transfer data from FPGA to PC zith FT_read(). and then continue transfer the next 4K data from PC to FPGA . In HDL code: if rxen = 0, then oen = 0 , then rdn = 0, strart to receive data on FPGA, if the data size = 4K and txen = 0, start to send data on FPGA, wrn = 0; if the data size = 4K , jump to next receive state. First problem, the process will lose 2 bytes data every 510 bytes data, that mean i can not receive the 511st the 512 byte data; Second problem, i can not write the 4K data into the FPGA, the application show that the "write bulk fail" , but i can write less than 510 bytes data into the FPGA and read back currently; it is current to finish transfer data at one direction, such as just transfer data from PC to FPGA or transfer data from FPGA to PC, no matter how many bytes. I wonder if someone with some experience of this could give me a few pointers. Thank you very much for you help.
  7. Hello all, I am using Nexys vedio FPGA board, facing a problem in Vivado 2016.1. I used the FT_prog to erased FT2332HQ by accident, and the vivado shows that [Labtoolstcl 44-469] There is no current hw_target. I have reinstalled FTDI and cable drivers once again, but no work. any other suggestion to solve this problem. @Bianca