macgyverque

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About macgyverque

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  1. @jpeyron Just checking in. I think the forum went down some time last week and I was pinging you to see if you had a chance to look over the attached system diagram and BSD. I've finally got a moment to jump back on this and will work on it later tonight. Thanks for your help
  2. Hey @jpeyron, thanks for spotting the post and verifying on your end. I ran the xintc_example and it actaully gets past the XIntc_SelfTest! Unfortunately, the program is stuck in the while loop waiting for the InterruptProcessed flag to be set. This is great progress though! Why do you think it may be getting stuck considering i'm using the base SDK and code? As an aside.. Not sure why i'm running into such odd issues. Almost want to compare this to the Pynq board to see if my board is somehow damaged, but the default bitstream that comes flashed on the ROM likely has interrupts so I'm wondering if there's an issue w/ the SDK or my implementation of xintc in Vivado. Difficult to get started when the default apps don't work. Arty-BSD_SDK.tgz
  3. Hello All, Have been attempting to enable interrupts on a project using the Arty and was running into issues with the intc_SelfTest failing. I loaded the Arty BSD from github thinking I had some issue with the project itself but am getting the same exact result. Any suggestions as to what I may need to change? I changed nothing in the BSD so I'm assuming it should be correct. Also followed multiple online tutorials and have been unable to solve the issue. All suggestions are greatly appreciated. Thx!
  4. @jpeyron Thanks a million! I was able to modify my project and get both UARTs working simultaneously!
  5. Ha! I just happened to click that and noticed it . Chomping at the bit to attack this again and replicate your results. I'll be back on shortly.
  6. @jpeyron Thank you so much for your time. I've been questioning the known universe trying to figure out why I can't send data out of a uart which is one of the simplest tasks to accomplish. I opened the project you attached last night and it upgraded the majority of the IP modules due to my version of Vivado being newer. I didn't observe the data being output on the TX line using my TTL/UART interface but I'll attribute that to an oversight on my end and will try again this evening and report back. One observation from your block diagram is that you have separate RX and TX lines coming from your uartlite module while I have what appears to be a port. I think this is a difference in either the version of Vivado or the IP. On the uart_0 IP it's setup to use the usb_uart board definition while the uart_0 IP is setup to use a custom interface. I attached a couple pics to show the delta.
  7. Trying to instantiate multiple UARTLite cores in a microblaze design using an Arty Board. For some reason, the output of both UARTLite modules is going through the same USB UART port as opposed to the second port I've configured. Any suggestions? [CONSTRAINTS] set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_rxd] set_property IOSTANDARD LVCMOS33 [get_ports usb_uart_bc127_txd] set_property PACKAGE_PIN U11 [get_ports usb_uart_bc127_txd] set_property PACKAGE_PIN V16 [get_ports usb_uart_bc127_rxd] [SOURCE CODE] #include "xparameters.h" #include "xstatus.h" #include "xuartlite.h" #include "xil_printf.h" /************************** Constant Definitions *****************************/ #define UARTLITE_DEVICE_ID_0 XPAR_UARTLITE_0_DEVICE_ID #define UARTLITE_DEVICE_ID_1 XPAR_UARTLITE_1_DEVICE_ID #define TEST_BUFFER_SIZE 16 int UartLitePolledExample(u16 DeviceId); /************************** Variable Definitions *****************************/ XUartLite UartLite_0; /* Instance of the UartLite Device */ XUartLite UartLite_1; /* Instance of the UartLite Device */ /* * The following buffers are used in this example to send and receive data * with the UartLite. */ u8 SendBuffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */ u8 RecvBuffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */ int main(void) { int Status; /* * Run the UartLite polled example, specify the Device ID that is * generated in xparameters.h */ Status = XUartLite_Initialize(&UartLite_0, UARTLITE_DEVICE_ID_0); if (Status != XST_SUCCESS) { return XST_FAILURE; } if (Status != XST_SUCCESS) { xil_printf("Uartlite polled Example Failed\r\n"); return XST_FAILURE; } Status = XUartLite_Initialize(&UartLite_1, UARTLITE_DEVICE_ID_1); if (Status != XST_SUCCESS) { return XST_FAILURE; } if (Status != XST_SUCCESS) { xil_printf("Uartlite polled Example Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran Uartlite polled Example\r\n"); //XUartLite_Send(&UartLite_0, SendBuffer, TEST_BUFFER_SIZE); int temp = 80000; int simplecounter = 0; char links[] = "DIGILENT DIGILENT\n\0"; char linksx[] = "ARTY ARTY ARTY ARTY\n\0"; while (1) { if (1) { xil_printf("Cha Cha Cha.... %d\r\n", simplecounter++); XUartLite_Send(&UartLite_0, &links, TEST_BUFFER_SIZE); XUartLite_Send(&UartLite_1, &linksx, TEST_BUFFER_SIZE); temp = 80000; } } return XST_SUCCESS; } [XPARAMETERS] /* Definitions for peripheral AXI_UARTLITE_0 */ #define XPAR_AXI_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_AXI_UARTLITE_0_HIGHADDR 0x4060FFFF #define XPAR_AXI_UARTLITE_0_DEVICE_ID 0 #define XPAR_AXI_UARTLITE_0_BAUDRATE 9600 #define XPAR_AXI_UARTLITE_0_USE_PARITY 0 #define XPAR_AXI_UARTLITE_0_ODD_PARITY 0 #define XPAR_AXI_UARTLITE_0_DATA_BITS 8 /* Definitions for peripheral AXI_UARTLITE_1 */ #define XPAR_AXI_UARTLITE_1_BASEADDR 0x40610000 #define XPAR_AXI_UARTLITE_1_HIGHADDR 0x4061FFFF #define XPAR_AXI_UARTLITE_1_DEVICE_ID 1 #define XPAR_AXI_UARTLITE_1_BAUDRATE 9600 #define XPAR_AXI_UARTLITE_1_USE_PARITY 0 #define XPAR_AXI_UARTLITE_1_ODD_PARITY 0 #define XPAR_AXI_UARTLITE_1_DATA_BITS 8 /******************************************************************/ /* Canonical definitions for peripheral AXI_UARTLITE_0 */ #define XPAR_UARTLITE_0_DEVICE_ID XPAR_AXI_UARTLITE_0_DEVICE_ID #define XPAR_UARTLITE_0_BASEADDR 0x40600000 #define XPAR_UARTLITE_0_HIGHADDR 0x4060FFFF #define XPAR_UARTLITE_0_BAUDRATE 9600 #define XPAR_UARTLITE_0_USE_PARITY 0 #define XPAR_UARTLITE_0_ODD_PARITY 0 #define XPAR_UARTLITE_0_DATA_BITS 8 /* Canonical definitions for peripheral AXI_UARTLITE_1 */ #define XPAR_UARTLITE_1_DEVICE_ID XPAR_AXI_UARTLITE_1_DEVICE_ID #define XPAR_UARTLITE_1_BASEADDR 0x40610000 #define XPAR_UARTLITE_1_HIGHADDR 0x4061FFFF #define XPAR_UARTLITE_1_BAUDRATE 9600 #define XPAR_UARTLITE_1_USE_PARITY 0 #define XPAR_UARTLITE_1_ODD_PARITY 0 #define XPAR_UARTLITE_1_DATA_BITS 8
  8. Hello, I've recently purchased a PYNQ-Z1 dev board and am working to follow the examples in the Adam's MicroZed Chronicles. I'm able to successfully create the reference design in Vivado consisting of only ZYNQ PS, generate bitstream, Export HW Design and also create software projects that run on the target device in the SDK via JTAG. When attempting to create the boot image and flash, I've been unable to get the anywhere via QSPI or by placing the .bin file directly on the SD card and using the SD boot option switch. Here are the steps I've taken thus far: Create new Vivado Design project referencing the Digilent Arty-Z7-20 Board Added the ZYNQ PS Connected M_AXI_GP0_ACLK to FCLK_CLK0 and fast foward....generated Bitstream Exported HW Design Create Sample Hello World Project in SDK (tested successfully and runs perfectly via JTAG) Generate FSBL Create Boot Image - Added elf bootloader from FSBL - Added bitstream from HW Export -- This generates the bin file used to program flash in the next step Program Flash - Selected the HW Platform Exported from Vivado - Used Image file created above - No Offset - Flash Type qspi_single Flash programming completes successfully. I select QSPI, power cycle the board and fail to get the done LED on the board indicating that the FPGA bitstream has been downloaded. I place the same bitfile named boot.bin on the SD card and get the same result. Nothing. Any suggestions? Is there some strange delta w/ the Digilent board I'm using that I don't know about. Additionally, the example bin file provided by Digilent works perfectly.