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  1. bino

    Connect my IP module

    Thank you, very much for your comment ! Yes, I read and understood connected examples by Xilinx. I have no problems to drive leds directly from SDK via AXI GPIO. But no success to run my IP block (but IP block work fine out of this design). The warning, that worn me a bit is : WARNING: [BD 41-1306] The connection to interface pin /axi_gpio_0/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO when connected 8-bit output of GPIO to IP ... Here is c source from SDK : #include <stdio.h> #include "platform.h" #
  2. bino

    Connect my IP module

    HI ! First : I'm a new in FPGA development For my experiments, I designed an IP module (in Verilog), which takes 3 inputs (clk, rst, walk[7:0]) and drives in funny way leds. Decided, that it's too much for this to use AXI memory mapped interface and used for control signal only 8-bit vector. My question is : can I use AXI GPIO with 8 bits output and connect only it's output vector to my IP's "walk" ? As I tried, the default value from GPIO works, but couldn't drive this value from the SDK at the address of the AXI GPIO ? Or may be some more clean way ? Sorry, forgot : I test the d
  3. I use Zybo too ... Just my 2 cents ... Are you use the logic push buttons (which generates terminal messages with this demo) or only try the switch buttons on the left down ?
  4. I'm a new member of this forum and another one, who got started with Mojo and come to Zybo ! With a big experience with C/C++ programming, UNIX administrating and developing software applications for different platforms. From a few month ago, my new passion is FPGA and SOC ... I'm sure I'll find here the answers for my future questions ! Thank you in advance ! Regards to all ! Branimir