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  1. Still more on this...the Vivado Bitgen completed the Digilent bsd project successfully when I made the above correction to the part0_pins.xml file. I'm wondering if anyone else actually ran this project or if this error has just been out there since the project was generated. I suppose someone could have messed up the file but that seems unlikely. Now I need to figure out if the Check Timing warnings (80 no_input_delay and 76 no_output_delay) with High Severity are of consequence or not. If they are I guess I'll need to find a way to fix that. Any ideas?
  2. More on this...I just noticed that CK_SS on the Digilent Arty schematic is FPGA location C1 NOT V17 as specified in the file "c:/Xilinx/Vivado/2015.4/data/boards/board_files/arty/C.0/part0_pins.xml". I'll try making that correction and see if all goes well.
  3. Thanks for the reply. I was thinking along the same line but since I'm a newbie at Vivado I'm not sure how to proceed with a fix. I thought that the Digilent project would be a slam dunk example like the other two (Xadc_demo and GPIO) which completed fine but apparently there are some bugs in the bsd project that haven't been fixed. I looked at the file "c:/Xilinx/Vivado/2015.4/data/boards/board_files/arty/C.0/part0_pins.xml" and found that <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="V17"/> and <pin index="93: name ="spi_ss_i" iostandard="LVCMOS33" loc=
  4. When trying to run the Digilent bsd project for Arty, Vivado 2015.4 cannot run Bitgen due to 2 critical warnings. I have been able to run the Digilent Xadc_Demo and GPIO projects successfully with no problems. I'm wondering if there is an error in the .tcl script for the bsd project. I've attached the Vivado critical warning messages. I'm new to both VIvado and Arty so I would appreciate help.