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  1. @jpeyronļ¼Œ Hi, I have successfully got the data transferred. Thank you very much for your help! However could you tell me what function of the vivado you have used to produced the waveform the above pictures you attached? best wishes! Sophia
  2. @jpeyron Hi, I conduct the demo project the "Zybo XADC Demo" you attached, and the circuit is as follows,my project attached follows, when I switch up , the led bright but don't change. when I load the program into the board ,there is a problem: [Common 17-48] File not found: E:/fpga_test/ad_testpl_2_board/test/test.runs/impl_1/debug_nets.ltx best whishes! sophia XADC.v ZYBO_Master.xdc
  3. Hi @jpeyron I have read the forum, but don't solve my problem, the simulation well done now, the constraint file is as follows. And I connect a 0~1v voltage to auxp7, but auxn7,vn,vp are connected to ground. I only used the aux7. The settings of XADC are: Independent ADC Mode; Continuous mode; sequencer mode is off; channel averaging is 16; enable external mux is false; ZYBO_Master.xdc
  4. Hi, I am using XADC on Zybo board in external valtage in 0~1v is used. A simulation on the XADC is successful to be done,the results of transformation are correct. However, when I connect a external power to the pin, the result as showed on LEDs is wrong and the drdy is always zero .Is it the constraint wrong? My constraint is as follows. the pin2 as vauxp7 is connected to external power. the pin8 as vauxn0 is connected to GND. thanks for help! Sophia.
  5. Hi, The data width of BRAM is 32-bit,if I transfer data to BRAM in SDK,can I use the function Xil_Out8 or should Xil_Out32 ? Regards, Sophia
  6. I have built a program in PL and PS with vivado. Then I generated a bitstream and launched sdk.All settings were done,when I program FPGA in sdk,there were some problems. 09:27:17 ERROR : Unknown processor type ps7_cortexa9 while tryingto figure out bootloop path 09:27:17 ERROR : Unknown processor type ps7_cortexa9 while tryingto figure out bootloop path 09:27:27 ERROR : FPGA Configuration failed.Failed to download the bit file
  7. @[email protected] I made a fool mistake...I didn't make the B port enable...I thought I set it 'always enable'. I think I need more carefulness.Thanks for your help very much!
  8. @[email protected] I tested it in the last version,but failed again. In the last wave as it shows , I lifted the WEA at second period, and dropped the WEB. Then I wrote datas to sequent addresses. at the same time readed from B port. However, the data from B is also zero. That's my testbench. `timescale 1ns / 1ps module test_bram; // Inputs reg clka; reg [0:0] wea; reg[0:0] rsta; reg [3:0] addra; reg [15:0] dina; reg clkb; reg [0:0] web; reg [3:0] addrb; // Outputs wire [15:0] doutb; // Instantiate the U
  9. @[email protected], I tried again, but the result is so frustrating. I can't agree you more.I think I can try it in another version of Vivado... Sophia
  10. @[email protected] You are so humorous,haha... yes ,I want to use A port as input to write data, and B port as output to read data, so I tried again and again ,but failed again and again...
  11. Hi, I want to test the IP core---BRAM,that has true dual ports,portA is 'write first','always enabled',portB is 'read first','always enabled'.Untick the'common clock'. In the testbench, wea=1,web=0;there are two source clock---clka and clkb that'periods are 8ns respectivly.In addition, The interface of BRAM is blk_mem_gen_0 uut( .clka(clka), .wea(wea), .addra(addra), .dina(dina), .douta(), .clkb(clkb), .web(web), .dinb(), .addrb(addrb), .doutb(doutb) ); for address and data, #0 wea=1; web=0; addra=0; dina=0; #10000 addra=1; dina=
  12. Hi, I want to use Zybo to realize a function---read from Bram one by one in PL.The data in BRAM is transfered from PS7.Can I program PS7 in C, program PL in verilog,and use the IP--BRAM? Regards, Sophia
  13. Hi, I am using ethernet of Zybo,and want to utilize lwip to realize tcp,however,how can I obtain the data reveived from raw api and save it in BRAM or distribute ram? Regards, Sophia
  14. Hi I want to utilize sdk to test echo server lwip,fpga program and run configration are done.However,in console,there are some lines make me confused. -----lwIP TCP echo server ------ TCP packets sent to port 6001 will be echoed back link speed: 1000 DHCP Timeout Configuring default IP of Board IP: Netmask : Gateway : TCP echo server started @ port 7 When I ping the board on PC,it displays "can't access the destination host" My board is Zybo.The hardware been built in vivado 2014.3.1 is a Zynq