jamey.hicks

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jamey.hicks last won the day on March 17 2017

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About jamey.hicks

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  1. Vivado slowness reality check

    Vivado is not fast, but it's a big improvement over its predecessor (Xilinx ISE). I found Altera Quartus to be quite slow also. You can enable reuse of place and route results when you make small changes to the design and that will save some time during development. It still has to do synth_design and opt_design before reusing placement/routing results, but it does save time. Build times increase with design size, but they increase faster if the toolchain has to work hard to try to meet timing constraints.
  2. Axi DMA timing

    Nice job! I'm happy to hear that you got it working.
  3. Axi DMA timing

    Take a look at the configuration options for DDS -- it has an option to enable the tlast pin on the AXI stream interface.
  4. Axi DMA timing

    The aclk of dds_compiler_0 should be the same as the m_axi_s2mm_aclk, judging by the pinouts. It confuses me that tlast is coming from a clock generator. Shouldn't it be driven by an output from dds_compiler_0 along with tdata and tvalid?
  5. Axi DMA timing

    You should use the 2Hz clock for m_axi_s2mm_aclk, otherwise, I expect you are seeing approximately 83000/2 repeats of the same value. The tlast value should also be driven from the same clock as tdata so that it will be in sync as well.
  6. How to modify Zybo Master.xdc to use inbuilt clok?

    Isn't that the clock source that is used by the Zynq internal PLL's? If so, it is used to produce the 4 fclks that are available directly to the PL (programmable logic). The frequency of each fclk is controlled by control registers that can be modified from a device driver.
  7. Project using PS alone on zynq

    What kind of software environment do you want to have on the board? Which zynq board are you using?
  8. Pmod Wifi board with Basys3

    Is source code available now for the pmod WIFI?
  9. I haven't used the JDK on zedboard or zybo, but I did run Android on zedboards and was able to get its GUI to display, which uses quite a bit of Java. Android really needs a GPU, which zynq does not have, so I do not recommend this path for a GUI. If JFRAMES works in Ubuntu 16.04, you might be able to run it on the ARM processor of a zybo, if you run Ubuntu on the zybo. In this case, you only need a small program to run on the zybo. Another option, if you have some skill with networking, is to run your UI on another machine and stream the data to it over ethernet from the zybo. If you know javascript, websockets is a good option for interaction between the GUI and a small amount of code on the zybo.
  10. File system in vivado SDK to run on ZED board

    I don't use the Xilinx SDK because I prefer to run Ubuntu or Android on zedboard, zybo, etc. Ubuntu works really well because so many prebuilt packages are available and it's so familiar to developers. With either of these, filesystem access is available as usual.
  11. The Zybo's USB to JTAG interface

    I have seen some code that enables the use of FTDI 2232 and openocd with the Xilinx tools, but it required more steps than I wanted to go through to install it. If you want to use Chipscope / Integrated Logic Analyzer, at the moment I would recommend using the Digilent JTAG SMT module. It's well supported in the software. If you're going to use an FTDI chip, I recommend FT2232 because you can support JTAG and serial connections with one device. That is also true for at least one of the Digilent JTAG SMT modules. If you just want to program over JTAG you can use openocd (I have only tested this with Spartan 6 but it claims to support Zynq). The FT2232 datasheet documents the use of MPSSE mode for JTAG and SMT. Well, it documents the pinout for those modes.
  12. Programming multiple FPGA in remote production machine

    Daisy chaining the transmitter boards on JTAG will work and then you can program them all using the SMT JTAG module. I can see cost being a consideration for not including the JTAG module on each board, but I would think it would be better to use a larger FPGA and fewer boards if you wanted to reduce the cost. Just out of curiosity, how are you communicating with the Spartan FPGAs?
  13. How to make I2C probe like commands working in u-boot

    This would be much easier from Linux using i2cget and i2cdump, which can be run from the shell: https://linux.die.net/man/8/i2cget
  14. Can I program zybo in PS and PL?

    It sounds like you want a BRAM FIFO rather than a BRAM.
  15. SD card trouble in Zybo

    The FAT32 partition has to be the first partition, but it sounds like that is already the case on your card. I forget the details, but your boot.bin does have to include somePS7 configuration and signal routing for booting from the SD Card on Zybo In my project, we generally do not include a bitstream in boot.bin but load it from Linux to enable faster reconfiguration. However, for Zybo we had to include a very simple .bit file in boot.bin. Here is the files we used to generate the initial Zybo bitstream, in case it helps: https://github.com/cambridgehackers/zynq-boot/tree/master/bitfile/zybo