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About jamey.hicks

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  1. I'm going to echo @xc6lx45 and suggest that you reconsider. Does your Kintex have insufficient BRAM for an on-chip FIFO? Using BRAM would be so much easier. If you choose to use the external FIFO, you'll have to adapt the logic that you use to interface to the FIFO to use the signaling of this other FIFO. Sometimes it helps to post more context: what do you want the system to be able to do that it does not now?
  2. To solve a timing problem, you need to dig into the timing report. From your screenshot, we can see there are failing intra-clock timing constraints on clk_fpga_0. In order to resolve the failures, you need to look at what paths are failing. You posted the .rpx file but it's easier to look at the report outside Vivado.
  3. I've never tried this, but I believe that your logic can communicate via AXI to the built-in USB controller, which can operate in device mode. This would take fewer PL resources than using the AXI USB 2.0 Device Controller. To do so, you'll need to remove the USB controller from the device tree file used to boot Linux so that only your PL would be using the USB controller.
  4. jamey.hicks


    Hi @sourav, What sampling rate do you need for your analog signals? What kind of ADCs do you plan to use? As @zygot says, you do not have enough pins for 40 parallel ADC connections, but if your required sampling rate is low enough you can multiplex the digitized data on a smaller number of pins. If the sampling rate is too high you might need to use a bigger FPGA. Cheers, Jamey
  5. Hi, Your insight about inserting of registers increasing the amount of work done is basically correct. Pipelining does add overhead. However, as shown by the cookie baking and car building examples, using pipelines may increase throughput -- the amount of work done in a unit of time. If you look at the the design of speculative, out-of-order CPUs, you can see how extreme it can get in terms of using more energy per instruction in order to maximize instructions per second. If you start with RTL written in Verilog, VHDL, Chisel, or Bluespec, pipelines are inserted by the developer
  6. jamey.hicks


    I don't know if any of the FMC pins connect to XADC, so pretty much all the signal pins are digital. Some are capable of differential signaling and some are routed for clocks. The reason I suggest the schematics rather than the FMC spec is that it depends on what kind of FPGA pin the FMC connector pin is connected to. According to the FMC spec, LAXY_P and LAXY_N would be a differential pair, but they might not be connected to a differential capable pair of pins on the Zedboard. Furthermore, it's safest to develop basic FPGA logic and provide an xdc constraint file with the desired p
  7. jamey.hicks


    I find the schematics to be very helpful when dealing with FMC pins or other I/O pins connected to an FPGA. The Zedboard schematics and other specs are available here: http://zedboard.org/support/documentation/1521
  8. Vivado is not fast, but it's a big improvement over its predecessor (Xilinx ISE). I found Altera Quartus to be quite slow also. You can enable reuse of place and route results when you make small changes to the design and that will save some time during development. It still has to do synth_design and opt_design before reusing placement/routing results, but it does save time. Build times increase with design size, but they increase faster if the toolchain has to work hard to try to meet timing constraints.
  9. jamey.hicks

    Axi DMA timing

    Nice job! I'm happy to hear that you got it working.
  10. jamey.hicks

    Axi DMA timing

    Take a look at the configuration options for DDS -- it has an option to enable the tlast pin on the AXI stream interface.
  11. jamey.hicks

    Axi DMA timing

    The aclk of dds_compiler_0 should be the same as the m_axi_s2mm_aclk, judging by the pinouts. It confuses me that tlast is coming from a clock generator. Shouldn't it be driven by an output from dds_compiler_0 along with tdata and tvalid?
  12. jamey.hicks

    Axi DMA timing

    You should use the 2Hz clock for m_axi_s2mm_aclk, otherwise, I expect you are seeing approximately 83000/2 repeats of the same value. The tlast value should also be driven from the same clock as tdata so that it will be in sync as well.
  13. I'm pretty sure you need to flash a boot.bin image containing your fsbl.elf and system_wrapper.bit rather than flashing the individual files. The boot.bin file contains a simple header and then the binary file sections so that the FSBL in the Zynq ROM knows what to load and where.
  14. Yay! Source! https://github.com/Digilent/vivado-library/tree/master/ip/Pmods/PmodWIFI_v1_0/drivers/PmodWIFI_v1_0
  15. I've been using a Spartan6 with an FT2232H to program the board via openocd. You need a recent enough version of openocd to have Spartan6 support. I believe the Digilent programming module also uses an FTDI chip, in which case openocd should work. If it's an FT2232 there are two JTAG channels. If you try each one you should be able to enumerate and program the FPGA. Looks like you need the latest openocd release: 0.10.0 http://openocd.org/ I have an Ubuntu package built for amd64 and armhf in the Connectal PPA: https://launchpad.net/~jamey-hicks/+archive/ubuntu/c