tuan

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Everything posted by tuan

  1. Dear all I need to make a 1080p60Hz SDI to RGB system, then sending the RGB data to PC via Ethernet. I use a SDI to HDMI converter and ZYBO board to do so. On ZYBO board, I used Xilinx DVI Receiver (SelectIO Interface as shown in the attached image) IP to receive TMDS signal before decoding to RGB image and write it to 2nd half of DDR memory (256MB from address 1000_0000). Xilibus core and the corresponding provided embedded linux are used for other control (SD card, Ethernet) and communication. OS is located in the first half of the DDR memory (256MB from address 0000_0000
  2. Dear miguel In your tutorial, you said that the code modified during OS preparation will divide the DDR memory into 2, a half for OS, and the other half for DDR. "What this does is make Linux see only 256MB of DDR memory (instead of all the 512MB capacity that the DDR has). This is required in order to have a chunk of memory (in this case, 512-256=256MB) reserved for using the AXI DMA engine.". It seems that OS will not touch to the second half. Are there any possibility to make OS reads the second half of memory but still allows user HW writes to it. Problem of read during write mig
  3. Hi JColvin Thank you. It is completely my checking problem on the page. Tuan
  4. Hello miguel Thank you for your instructions The problem is not there since setting64.sh is executable. I found the problem related to a 32bit library, which must be installed manually: la32-libs. However, I have a problem that is the Vivado on Ubuntu generated error during optimization for implementation as attached file. [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'xillybus_ins/system_i/vivado_system_i/xillyvga_0/inst/xillyvga_core_ins' of type 'xillybus_ins/system_i/vivado_system_i/xillyvga_0/inst/xillyvga_core_ins/xillyvga_core' has undefined contents
  5. Hi miguel I am following your instruction and also the link you gave on how to booting linux on zybo (http://www.dbrss.org/zybo/tutorial4.html). I clean install Ubuntu14.04.5LTS and Xilinx2015.4 on Virtual Box for this purpose. At step 2, after "make zynq_zybo_config", make command gives error as shown in the attached error.txt file. The first path with "No such file or directory" error is confirmed that it is available as shown in the "path_available_confirmed.txt" It is noted on the tutorial: "If you get an error during this step your $PATH environment variable most likel
  6. Dear miguel_rodrigues I just look through your tutorial and related links. I think they can help me to solve the problem of integrating with Linux OS. I will ask you if I have problem during that process. I still have some problems related to input devices. My design will be used with some device with 1080p output (it is said so). For my testing, I have a sony handycam HDR-CX180 with HDMI out, a blackmagic microConverter from SDI to HDMI, a 3G SDI to HDMI from BLUPOW, a multi format converter XC 1 so. All of them show on display as HDMI 1080p. However, signal from the former 2 c
  7. Dear miguel_rodrigues Thank you very much for your solution. I also have some advances in the project but some how in a different manner and would like to ask your experience on some problems that I will need to solve. A. Related to implementation: 1. How to write data to memory: I have a HDMI => RGB converter (with some additional processing will be required from now on) and I also have an interface for writing the generated data to DDR via PS. My AXI interface connects with S_AXI_HP0 of PS (I include my design into the block design of the xillydemo project), so that it
  8. Dear Jon Thank you very much for your help in finding expert on this issue. Best Wishes, Tuan
  9. @Dan Thank you for many links and comments on location of user memory. I understand the problem of locating my HW data at physical location 00000000 and that is why I mention that it is unreasonable since it will cause conflict with OS. My design writes data to memory using AXI bus and via AXI_HP0 port of PS. Since ILA (without OS operated) shows changes in address generated for AXI writing (to that memory space start from 00000000), and in other testing case, OS starts and normally operates (without ILA monitoring), I suppose that when OS operates, it prevent my design from writing
  10. Dear jpeyron

    I am Tuan. Dan said that you are expert on embedded Linux aspects of FPGA programming and I have some questions to ask.

    I am developing a design based on xillydemo for ZYBO board, in which my hardware will write image to DDR on ZYBO, then OS (Ubuntu) will read those data and write to file. Current situation is the writing HW (my part) can write data to memory without OS work (I check that the generated address for AXI bus has change via ILA, so PS works but not OS). I assign my design to address 00000000, which I think that OS will over taken when it works (but I don't know where is a good space for my data). The combined design (my HW and xllydemo) shows that OS are normally working but I cannot check if my design successfully write data to memory or not.

    Do you have any suggestion about how can I manage the physical memory? or which physical memory space should I consider as user allocated space by Ubuntu? I find some pages say about directly assess to physical memory from OS using /dev/mem and mmap. Do you know how can I check information on /dev/mem and mmap to know which physical memory are assigned to which device as well as which spaces are assigned to user and also how can I make a physical memory reading from OS in this case (mass reading about 6 MB each time)

    My email is [email protected]

    The related thread can be found in the link below.

    Thank you very much

    Tuan

     

  11. Thanks Dan I search for the direct reading solution and also found some how similar information you provide, which said that we can direct read and write to physic memory using /dev/map via mmap but my problem is I cannot find how can I check the information about various devices available inside (I develop current design from the xillydemo project). My knowledge on Linux is low, and so I am confused in checking the correct way to use and understand the mmap as well as how Linux control the user memory. Now, I temporary assign my design (HW) to physical memory from address 0. Big image w
  12. Hi [email protected] Thank you for your reply. I try so max delay and min delay setting to solve the hold time violation problem and it works. Data transfer from the slower clock domain (74.25MHz) to faster clock domain (200MHz). The min time delay is set to a half the time of the faster clock (2.5ns) and max time delay is equal to 1 faster clock (5ns). With that, I thrown away 1 clock of the faster. This seems not a really good solution because situation may be changed if difference frequencies are used. Your solution is completely good but I have to strictly control the amount and time of data t
  13. @[email protected] Thank you for valuable document. Concerning to the FIFO, the problem does not happen with the FIFO itself but happen with user designed registers, which are used to communicate about the maximum number of data should be read from FIFO before stop and waiting for the next line. I am trying on this and will report if I found some possible solution. Best Regards.
  14. Dear everybody Dear jameu.hicks Thank you very much for your reply and sorry for my late feedback. I have a mistake in my first post. We need to read RGB data generated from HDMI input, and so DRAM is also good to me. I found a design in Japan which write RGB data to vram via AXI bus so that other module can read and show on display while PS also can access to this data. However I have timing violation problem in synthesis and implementation, that is hold time and setup time violation occur between registers belong to different clock domain (74.25MHz for DVI and 200MHz
  15. Dear everybody. Thanks DIGILENT for their very nice demo on HDMI => VGA converter on ZYBO. I would like to use ZYBO to convert input HDMI image to VGA output and also write result to BRAM for later use. PS should also work in parallel reading those result out (from memory) and written to somewhere via Ethernet. As my understanding, the demo given by DIGILENT for HDMI => VGA converter uses no BRAM. I would like to know if some similar (to my purpose) demo is available and where on the design should I modify to achieve the above purpose. Best Regards,