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  1. Hi, I am new to working with the Cadence Soc Encounter tool. I have generated GDSII file using this tool and by using FreePDK45nm files with the help of the user manual of cadence encounter . Now I have one question in mind, the question is"can we use two components of different technologies(say 180nm & 45nm) in a single design to generate GDSII file from verilog RTL code" .If yes please provide me a reference material .
  2. Can we connect 2 Zedboards using FMC-FMC cables directly? please provide solution ASAP n if possible any reference design?
  3. vvk

    Inter core communication

    Hi , My doubt is instead of using shared memory for dual core communication and some functions ,cant we divide the entire ddr memory in 2 parts ie some part of the memory for core0 and the rest for core1? Is it possible to communicate between two cores by doing as mentioned earlier? if not,can u please briefly discuss the reasons behind it.
  4. vvk

    Inter core communication

    Hi, I tried with the Zynq speed ways labs on dual cores communication and it is working fine. I did not understood the concept of onchip memory communication and the usage of semaphores(SEM). can u once briefly the usage of these functions in the software code.
  5. vvk

    Inter core communication

    Hi, I am attempting to have the two ARM cores in ZedBoard xc7z020 interact with one another via fpga (PL)core. Can anyone please give the valuable suggestion on the way to proceed to this task.I need to take the random data from PS_Core0 and put it on fpga and from fpga this has to go to PS_core1 of Zynq 7020 SOC.
  6. The design containing traffic generator ,aurora 64/66 b,Axi chip to chip IPs is synthesized successfully but the implementation is failing with out showing any error/ crictical warning. what could be the reason? please help me in resolving this issue.
  7. I am working with the ZYnq 7020 Soc and i am new to working with this board. In my project I want to transfer the data from Zynq PS section to PL section. I am unable to find how to do it by searching on internet.suggest me by providing any reference design/manual to achieve this communication.
  8. I am attempting to have the two ARM cores in ZedBoard xc7z020 interact with one another via fpga (PL)core. I want to send the data with a speed of 1Gbps from first ARM_0 core(PS) to ARM_1 core(PS) via PL, and the same data has to be loopback from ARM_1 core(PS) to ARM_0 core(PS) via fpga(PL) core. Kindly let me know how should i proceed for this.
  9. Hi I am working with zynq 7020 Soc. In my project I want to transfer block of data between FPGA to PS of Zynq soc. kindly help me by providing reference design .
  10. vvk

    Design with AXI TG ip core

    Hi, I am working with zed board.I am new to hardware design with ip core. I want to develop an hw design using AXI TG ip core in which I want to transfer the random data which comes from the ip core and receive the same data in buffer. Can any one please help me out how to create a block design for it by using available ip cores in Vivado 2015.2. please provide any referrence design too. Thanks in advance
  11. Hi, I am now trying to figure out how to realize data communication between FPGA and processor in the same Zed board. I have a couple of questions: 1) I know we can use FPGA write OCM on PS through AXI interface. We can easily enable an AXI HP port of PS in block design. But, how can we configure OCM rather than DDR as the destination? Also what AXI IP core needs to be used in PL? I find some uses AXI register slice, some uses AXI data FIFO. 2) What functions need to be used in the software so that the processor can read data from OCM? 3) Is there any reference design that helps me to complete my design? I have searched online and found that most of the reference design only introduced how to use AXI GPIO or how to use FPGA to write DRAM.
  12. I am working with zed board.please provide me with reference designs with AXI Traffic Generation IP core which should configured in slave loop back mode .
  13. Yes, I am trying to generate 1Gbps traffic between two ARM cores on the same ZC702 board. Actually i am trying to transfer the 1Gbps data from one ARM core to another ARM core and the same data has to be loop back with a same speed to another ARM core. Is it a possible in same zed board? please help me with the reference design. Another query i have is in order to generate the data with a speed of 1Gbps what is the optimum buffer size is required?
  14. HI, In order to generate 1Gbps of data i want to know what are the available ways ? Can a processor in the zed board generate 1Gbps of data or should i take data from axi traffic generator ip core and can i send this data to ARM core_1 and then transfer it to another ARM_core.
  15. I am working with zed board. zed board has one FPGA (PL) core and two ARM(PS) cores.Actually i am trying to transfer the data from arm_cpu_0 to arm_cpu_1 via fpga in zedboard but i cant able to get any reference design or lab on it. kindly let me know if any is available?.