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About takieddine

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  1. Hi @jpeyron I'm sorry to say this, but if digilent's advising to migrate designs form Atlys to Nexus Video board, but you didn't release a solution to interface VmodCam with the Nexus board, I hope that you take this issue into consideration in the future thank you, Taki Eddine
  2. Hi @jpeyron Is there a solution to interface VmodCam with the Nexus Video board ? thank you, Taki Eddine
  3. Hi all, Is digilent releasing a new stereo camera module that will be compatible with the Nexus video board ?
  4. Hi, In the atlys_rm_v2 doc page 14, it is mentioned " An EDK reference design available on the Digilent website (and included as a part of the User Demo) displays a gradient color bar on an HDMI-connected monitor", however I cannot find this project in the resource center, would you please give me this project ? Thanks in advance,
  5. Hi Jon, I am never used the edk tools, and I only have a basic understanding of XPS and SDK, I would like to design my own system depending upon the mentioned demo project, I need some guidelines of how to understand the tools, I am using EDK 14.7
  6. I downloaded the demo project of configuring SPI flash and DDR2 memories controllers from this link https://reference.digilentinc.com/_media/atlys/atlys/atlys_mantest3_initmemtest_clean.zip, I would like to use the two controllers for my own application, the problem is the project is not associated with a documentation that explains the steps required for testing the peripherals of the system, can you please guide of how to test the two components mnetioned above ?
  7. Hi, I am trying to use the videotiming controller provided in the VmodCam demo project to display static images on an HDMI screen, my problem is that the size of images used is different from the rersolution selected by the controller, can I modify the code to add a new resolution ?
  8. I read spartan 6 memory controller documentation, and I understood that the batches sizes are chosen according to the size of the FIFOs inside the memory wrapper; my question now can I use small BRAM FIFOs to buffer the video feeds from VmodCam, lets say I use size of 32 for both batches.
  9. Thank you Cristian, In the documentation it is mentioned that this project applies to rev D of the board, I have REV C can I use it ?
  10. Hi Jon, I have three questions about the reference VGA design, how do you select the size of the read and write batches ? constant RD_BATCH : natural := 16; constant WR_BATCH : natural := 32; How do you choose the ending address in the frame memory buffer controller ? in the given code we have if (pc_rd_addr1 = 640*2*480/(RD_BATCH*4)-1) then pc_rd_addr1 <= 0; And why do you convert to p3_cmd_pr_addr like this p3_cmd_byte_addr <= conv_std_logic_vector(pc_rd_addr1 * (RD_BATCH*4),30)
  11. Hi, Could you please explain how the read and write batches are used in the frame buffer controller ?
  12. I have another question, using VGA resolution which context is recommended, A or B ?
  13. Thank you very much, That 's exactly what I was intending to do, designing my own clock generator, I will proceed in the debuggin and see the results. Taki Eddine
  14. Hi Dan, Sorry for not replying as soon as possible, in my debugging I figured out that the signal "PLL_lock" is common between syscon and fbctl components, my guess here is that this is the signal that causes the issue discussed previously, any suggestions ? TE SAIDI
  15. Maybe I will use a digital oscilloscope to monitor the different clock domains, I think that will give a good idea of how to debug this clocking issue.