shashi

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Everything posted by shashi

  1. HI there, I have a simple HLS design which I exported as an IP Core to implement on my target. But I get the following error when I go ahead interconnecting the IP cores. Does anyone have any idea as to how I can work around this obstacle? I even tried changing the frequency of the ports, but the fields are inactive. [BD 41-237] Bus Interface property FREQ_HZ does not match between /matrixmul_0/INPUT_STREAM(100000000) and /axi_dma_0/M_AXIS_MM2S(200000000) [BD 41-237] Bus Interface property FREQ_HZ does not match between /axi_dma_0/S_AXIS_S2MM(200000000) and /matrixm
  2. HI artvvb, Thank you for the reply. The problem still remains unsolved. I have added Fixed point library from Vivado HLS but not seems to be working yet. It compiles and gives result but the values are random. I have attached my code here. Can you please help me in resolving this bug.? main.cc
  3. Hello there, I have developed a fixed point design, then an IP core for matrix multiplication using vivado HLS.I need to deal with fixed point data types in Vivado SDK to send data to a fixed point IP core.Does anyone has any idea of how can i go about.?Thank you
  4. Thanks for that long reply. what i understand is that the HLS design is not recommended for huge matrix operations which involves for lops. But the same thing can be accomplished in hardware using HDL , right? So should i go ahead with HDL? will it work for this task atleast? Thnak you..
  5. HI Dan, Thanks for the reply. Basically, i need to do operations on a huge matrix(say 128x100x360) using FPGA as an accelerator. So I am setting the ground for that. Is it accomplishable or tough to realize? what other tool can I use for accomplishing the same task on FPGA? Since I can easily implement for loops in HLS, I thought it would be a perfect fit for the problem that we are addressing. what do you say about it? Regards: shashi
  6. I modified the code. Still, the same error persists. Any idea where I am going wrong fundamentally? core_test.cpp
  7. Hello there, This time i have a very simple design in HLS which takes in a 3d matrix, multiplies with a constant and gives output. It works for [64][64][64] matrix perfectly, but not for [128][128][128] matrix. Again I get the segmentation fault. Can somebody help me to know what fundamentally going wrong.. Thanks for your halp in advance. i have attached my design files here: core.cpp core.h core_test.cpp
  8. Hi Dan, Thanks for the reply. I have attached here the entire design files and the error log to give you a good perspective of my problem. Can you please look into them and give me your feedback.? It would be a great help to me. Thanks in advance HLS_files.zip
  9. HI there, I have a zed board. Developing a design in HLS for algorithmic acceleration. When I run the c-simulation for my design in HLS , it is not run showing the following error: But when i do c-synthesis it synthesizes the design with synthesis report, where in under latency and interval I see question marks: '?' why this happens and how do i understand this behavior? How can i get it corrected? Thaks in advance
  10. Hi experts, If i use trigonometric(sin or cos) or math functions (pow, floor, ceil ) in HLS with fixed point design it gives me error: what is the workaround? Thanks in advance. mlem_csim.log gravity_csim.log
  11. Thanks for your reply. I have a Virtex 7 board too. Maybe i will try to implement on that if it is going to take a lot of BRAM.
  12. Hi there, I get this error when I run the C simulation in HLS to implement on zed board. I know that this error occurs when classes or class member functions are set as the top-level for synthesis. But i am not able to figure out where exactly i am going wrong. Can someone guide me here.?
  13. Thank you. I got some idea.
  14. Hi, I am relatively new to FPGA design. I have not used MMU. I just want to store a 20MB file in DDR3 and do some image processing operation on it. How will i make sure i am not using the memory which is already been allocated. I am not using Linux either. Thank you
  15. Hi there I just want to verify how to store float values in DDR3 of zed board. I have written a small code, but when i read from memory, i am not getting the correct answer. Is it correct? can someone help me? #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xil_io.h" #include "xparameters.h" #define DDR_BASEADDR 0x01000000 int main() { init_platform(); int i; float img[5] = {11.2345 ,17.2135 ,11.65 ,18.543 ,7.6789};
  16. Hi there, I have a zed board and i want store data into DDR3 for my application. The data is in .txt file. I stored it. But when i am reading the data , its giving the wrong values. Can someone help me? firstly, Is it correct what i am doing? thanks in advance
  17. Hello there, Can i use file systems in SDK? when i tried running simple example(shown below) on ARM(in ZED board), it is not giving me any results. Can someone please tell me why it is so? file.c
  18. HI Arthur, Firstly thanks a lot for replying. The procedure looks little complicated. But surely I will give it a sincere try. I got one other idea. I packaged my HDL file into IP core and planning to write an application in SDK to send an image. Is that a better idea? I need your expertise on this? Can you please help me since I am relatively new to this area? thanks again for your help. Regards shashi
  19. Hello there, I have developed an image processing algorithm using the system generator and Generated the HDL netlist. Now i need to send the image file to the Verilog code generated, and compute the output and measure the time. Can anyone please help me in understanding how i should, input the image, get the output and then measure the time of execution on ZED board? Thanks in advance.
  20. shashi

    Nexys 4 FPGA board

    yeah it works now ..thanks a lot for helping.. when exactly one should use USB UART , USB OTG and USB JTAG ?