silverwolfman

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  1. Thank you so much for the information, Dan.
  2. Hello, I am using the cmod s6 eval board as the reference for my prototype board. I wonder how many board layers do I need if I am going to use the same package like the cmod s6 package XC6SLX 4-2CPG196 does? In additon, when I use the iMPACT to reprogram the chip flash, it took me 12 min for burn the code in the flash, is there any suggestion I could speed up this process? Thanks,
  3. Thank you Ivoudour, The Warning goes away. you are correct, it is a Fclk / 2^(divider+1) divider, the compiling succeed without the warning. There is another issue when I try to burn the program into the NEXYS 4 board, it is my first time to use this eval board. It still not working as I slide the sw changing the input. I basically just use the "Configure Target Device" and program the device with .bit file generated from the design(when i program the chip, it went through without error message, so I assume it is not a chip or board damage). I have also tried the Adept software and this is not working as well. I use to have a CPLD eval board and this program process is working fine under ISE webpack without any issue.
  4. Hi Everyone, I am developing a design based on ISE 14.7, Artix-7 CSG324 NEXYS4 eval board. For testing purpose, I wrote a simple clock divider code as following, but the compiler keeps warning me: Line 31(red line): Result of 32-bit expression is truncated to fit in 1-bit target. The RTL schematic looks the same as I expected, If ignore the warning and program the eval board, clock frequency wouldn't change when SW0 - SW3 input changed. I wonder if it is because of compatible issue for the compiler(most people use vivado for artix-7)? But on the Xilinx website it says the ISE will support Artix-7CX7A100T. Please let me know if you guys have any suggestions, Thanks ahead. module CLKDIVIDER( input clk_i, input rst_n_i, input [3:0] divider_i, output clk_o ); reg [15:0] clk_cnt; reg clk_o_s; assign clk_o = (rst_n_i == 1'b0)? 0 : clk_o_s; always @ (posedge clk_i) begin if (rst_n_i == 1'b0) begin clk_cnt <= 0; end else begin clk_cnt <= clk_cnt + 1'b1; clk_o_s <= clk_cnt[ divider_i]; end end endmodule Updates: The code when through now without warning, but after burn the code into NEXYS4 ddr board, it is not generating the output when I change the input. Test.zip
  5. Hi Jon, These information are really helpful, Thank you so much!
  6. Hi everyone, I am new to the Xilinx CPLD XC2C54A, I bought a Cmod: Breadboardable CoolRunner-II CPLD Module recently and try to use the platform do some experiment for our design. However, besides DataSheet and Schematic I didn't see any tutorial or example projects available for this board on digilent's website. If possible, could someone point me to the resource that could help me learn about this Architecture? Any sample code, tutorial I could follow? Thanks ahead.