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  1. lukap

    I2S IP core and AXI DMA

    Thank you very much. I did however manage to get the ADI IP I linked to in my previous post working. I had to do some minor changes (removed the drain_process in the streaming tx and enlarged the period_len register). I am intending to post a link to a working project in a few days. Oh, and the number of bytes from the previous post should be (I forgot to consider the bytes per sample - integer): 5 s * 48000 samples/s * 2 (channels) * 4 bytes/sample Luka
  2. lukap

    I2S IP core and AXI DMA

    Hello. I'm doing a sound analyzing project on the Zybo board and I'm having hard time using the AXI DMA for transferring data from the I2S controller to RAM. I'm using the I2S controller from the Digilent's github. I am trying to do the data transferring "properly" with a DMA and as there are no PL330 examples to be found (at least not bare metal, which is what I'm doing), I'm trying to use the AXI DMA. However I can only get a few samples to the RAM. I don't really know if there's a problem in the I2S controller or in my configuration of the DMA, so I'd first like to know if I understand how the DMA works. I'm basing my code on the Xilinx' interrupt DMA example, so I think the initializations and similar are done correctly. What I'm unsure of is the following: I start the S2MM (Stream to Memory Mapped - I2S to RAM) transfer with the number of bytes to be transferred and expect the I2S controller to only output data when it has it (similarly as in the Zybo base system example, except that there the fifo status register is checked, but for the streaming interface I expect this to be taken care of in the IP). So if I want to transfer 5 seconds of audio, I start the transfer of 5 s * 48000 samples/s * 2 (channels) * 4 bytes/sample For now I then wait for the interrupt in which a flag is set, so that I know the transfer has finished. I expect this to last 5 seconds but instead it happens in a couple hundred ms (I don't have an o-scope) and only a few samples arrive. So is my understanding correct? Has anyone ever tried interfacing the I2S core to an AXI DMA?