Hello Zygot,
Thanks for posting this example, it is great - and the unique complete resource available for this board.
I just got a Cmod A7 board and tried to create a similar project (with some extra components specific to my application), I've designed with Virtex 7 and the Arty a7 board before so I thought I'd get it straight, however I have a problem with the uartlite, it gets stuck transmitting after the 6th or 7th character output. The TX Full flag is never released so it gets stuck there.
So I decided to use your project as base and work from there.
Following the instructions you provided it all works flawlessly (executing your app as is). Next I repeat the process but this time I have Vivado update the project and IP since I'm using 2019.1. In this case the only problem I had is that SDK by default generates a linker that places all sections in the external ram instead of the local BRM. This generates an error when programming the board. I just re-generate the linker script changing the sections to be placed in local BRM and then it works ok. Then I move some of my own project's code to yours and... it all works! Still, then I add my IPs and stuff to your project, and it all works.
However, it frustrates me that, as mentioned earlier, when I build everything from scratch the uartlite doesn't work properly. I compare my own project with yours and they seem so similar, the only difference are my extra IPs (which have nothing to do with the uart) and in your project there's an axi_mem_intercon connected to the external ram.
- Can you explain the reason behind adding the axi_mem_intercon?
- When you created your project did you have any problems with the uartlite? did you have to adjust anything in particular for your project of just followed the regular workflow?
Best regards and thanks again!
