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  1. Finally I was able to use the UART and the GIC, but for the UART I had to write a custom driver to directly access the configuration registers. It took me some time because the Zynq TRM is very hard to follow. It doesn't have a proper register specification section, I had to deduct the registers and bit definitions from the text. I still find using Xilinx's BSP unconvenient, one has to follow the methods decided by Xilinx's engineers which are not so well documented in first place. If a design departs from the pre-written examples it is a challenge to understand how the APIs interoperate.
  2. Same problem here, I have a Cora board and need to use the PS UART in interrupt mode to receive data. I use some sample code by Xilinx and from other Digilent projects but it doesn't work. Something I notice is that after I configure the UART and the GIC, I read the uart's IER and IDR registers, which should hold the enabled and disabled interrupt masks, and they are both 0. Furthermore, I tried to use XSCT to manually write them but they remain at 0. Either they are locker or, could it be, they don't exist because they must be enabled in the HW design. Yet I can't find any part of the Zynq PS configuration where the PS UART irqs could be enabled. There's a section to enable PL to PS and PS to PL irqs, but that's not the same as enabling the internal PS irqs. I notice little or no support for Cora boards at Digilent's website, even on Cora's page, the examples and resources are just links to those for other boards.
  3. @vicentiu I've marked your response as solution as it is the solution to my question. However I'd like to add that some repos, such as u-boot, are too old already, the builder fails in latest ubuntu or debian (using libssl 1.1, maybe there're more problems after this point). I haven't tried the linux repo but I'm afraid similar issues may arise Been Cora a new board customers expect Digilent to provide updated tools and more documentation resources.
  4. https://github.com/Digilent/linux-digilent https://github.com/Digilent/linux-Digilent-Dev
  5. Thanks for your answer. I found that Digilent's own github contains u-boot and linux and, according to the notes posted, they now support Cora Z7. This is great! Howeve when I try to build u-boot I get this KNOWN error: https://forums.xilinx.com/t5/Embedded-Linux/U-Boot-compile-error-dereferencing-pointer/td-p/794782 According to that forum, the issue happens when using the latest libssl (1.1.0). Would it be possible for Digilent to try and test with a system using the latest libssl and then fix this issue? For Linux I'm a little puzzled since there're 2 repositories in Digilent's github with similar names, so I don't know which one is the one I should use, I tried with the one updated more recently but can't find the Cora config file, maybe the usage is different than other builders? Thanks e
  6. I think the Cora Z7 has landed ok in the community, I see many posts about it here, however, overall, there's very little information online, besides it seems all focus is on using Xilinx' Petalinux. Has anybody tried to build Linux for Cora Z7 using buildroot? I rather use open source and tools so it'd be great to have some support in this regards. Thanks
  7. I'm seeing the same issue with Vivado 2018.3 and even using the latest board files (from april 18th 2019). Has anybody from Digilent actually tried to resolve? any clues so we can may resolved it by ourselves?
  8. Hello, Vivado 2018.3 fails during Implementation with error: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (17) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 17 sites. Term: rgb_led_tri_i[0] Term: rgb_led_tri_i[1] Term: rgb_led_tri_i[2] Term: rgb_led_tri_i[3] Term: rgb_led_tri_i[4] Term: rgb_led_tri_i[5] Term: rgb_led_tri_i[6] Term: rgb_led_tri_i[7] Term: rgb_led_tri_i[8] Term: rgb_led_tri_i[9] Term: rgb_led_tri_i[10] Term: rgb_led_tri_i[11] Term: led_4bits_tri_i[0] Term: led_4bits_tri_i[1] Term: led_4bits_tri_i[2] Term: led_4bits_tri_i[3] Term: and eth_mdio_mdc_mdio_i Background: This project has been working for a long time using Vivado 2017.4. But now we're moving to Vivado 2018.3 so I upgraded the project and hit this problem. I also tried re-making a basic project from scratch completely in 2018.3 but hit the same problem. The basic project was made with the steps in https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze-servers/start Searched online and found few similar cases but they all were resolved by getting new board files from Digilent, however I'm using the latest files already (from April 18th 2019). Can anyone @ Digilent try to reproduce and provide board files qualified for 2018.3 in Arty (ver. C) board? Thanks
  9. I got the Arty A7 board back in 2016 and got it with a voucher for 1 year of vivado updates, up to Vivado 2017.4. I've been using 2017.4 without problems all this time. The Arty A7 board seems to have been very successful for Digilent and Xilinx since they keep making accessories, upgrades and stuff from it. Even recently Arm opened the M1/M3 cores for use in FPGA, and they use the Arty board as reference/test board. However the feature requires Vivado 2018.2. I also got recently a Cora Z7 which also recommends to use 2018.2 (I'm using it with 2017.4 without problems too). So now I'd like to upgrade to 2018.2. But I can't get the design edition with my voucher neither I can afford to pay for it. I can only get the Webpack edition. Looking at https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html there seems to be no difference between Webpack and Design editions other than "partial reconfiguration" which I don't use. Is that so? Can I do the same stuff I was doing with 2017.4 Design with the 2018.2 Webpack? I do a lot of microblaze based designs, I run linux and have several custom IPs. I use Virtex 7, Artix 7 and Zynq 7000. Will I be able to migrate without problems? will I lose some functionality or some device? what will be lost? Thanks for any advise in this regards. e.
  10. I use the S3E Sample Pack board on a regular basis and found it really useful. It is great to implement glue logic for bigger projects, as a companion board to monitor or debug signals or to build tools and interfaces to help in demos. Most of the designs at my company use big expensive boards (e.g. virtex 7 vc707) which I don't like to carry with me when travelling or working remotely, having this little guy allows me to work, test and verify sections of my design remotely before implementing them on the bid guy. Having this board with picoblaze forms and ideal tool for many problems. Digilent offers the breadbordables which are good, but I still find them short of gpios for most designs. I understand they are targeted to small designs but still would be useful to have more pins accessible. There are many unused pins on them. The only problem with the S3E SP is that its bpi strataflash can't be programmed via jtag, so basically everything design you load to the FPGA is volatile, you need to upload it every time. I found in my old PC an application created by Digilent called "S3E SP Configurator Setup" which is used to program the strataflash (windows only), however the manual says that it can only use the "Jtag 3" cable. I don't know which cable is it, but my HSx JTag cables don't work. It would be great if somebody at Digilent could dig in and post the original packages and tools for this board. And, since all the stuff is old, hopefully post some sources so we can re-build the tools for other os such as linux or mac. Yet still I found that Xilinx posted, long long ago, an application that uses picoblaze to flash strataflash memories. I got a hold on one of those applications and with some modifications got it to work with my S3E SP. I've been using it for a while with success,now I can store my programs permanently in flash. So I thought that it may be of help for other people to have it - and if you have this board, to return you to use it. So here it is. It requires picoblaze 3 which I didn't include in the package since it is still available officially from Xilinx website even today. It includes a manual with instructions, this is the original manual which was for a different board but the procedure is the same. Hope it helps. s3esp_picoblaze_nor_flash_programmer.zip
  11. Hey sLowe and [email protected], thanks a lot for your inputs, not only answered my questions but also gave me great advise. thanks again.
  12. Years ago I purchased my Atlys board. At that time I had ISE webpack already installed on my PC since I used it on my other boards and also all my designs were state machine based hence this setup was enough and I didn't bother much about license matters. Today I'm using more complex boards and ublaze extensively. However, it always comes very handy to use my old boards to test portions of my designs before moving to the big system. Specially since this allows me to work from home without having to carry the -very expensive- boards. However the XPS in the Ise webpack (14.7) doesn't let me build a ublaze inside an spartan device due to licensing. Since this is for personal use, I can't spend several $k in a license. I really don't recall if my Atlys board included any other license, I don't have the original packaging. Can anybody in the forum using the Atlys tell me if it comes with a system design seat or how can I do to overcome this problem and use my board with ublaze? I have the same problem with my Nexys 2, my S3 starter kit, S3E sample pack and other old boards... It is really sad to think that I have to scrap all of them. BTW, I also would like to know if the Vivado Webpack has the same limitations for the new FPGAs (Artix-7, etc)? I'm considering getting the Basys3 but I'm wondering if I'll have the same problem. Thanks