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  1. My apologies, seems I got confused with the projects (like some others in this thread), I came here looking for "Cmod-A7-35T-OOB" support but seems landed in the wrong place. Again, apologies.
  2. Hello Zygot, Thanks for posting this example, it is great - and the unique complete resource available for this board. I just got a Cmod A7 board and tried to create a similar project (with some extra components specific to my application), I've designed with Virtex 7 and the Arty a7 board before so I thought I'd get it straight, however I have a problem with the uartlite, it gets stuck transmitting after the 6th or 7th character output. The TX Full flag is never released so it gets stuck there. So I decided to use your project as base and work from there. Following the ins
  3. Zynq PL-PS IRQ's are predefined as acting at rising edge/high level. When interfacing external devices, most commercial devices generate falling edge/low level. I've been inverting the polarities using verilog code, but it seems a little odd to me. I wonder if there's already a 'proper' way to deal with this situation, maybe I'm missing something since I don't see anybody mentioning this. Any advise?
  4. Finally I was able to use the UART and the GIC, but for the UART I had to write a custom driver to directly access the configuration registers. It took me some time because the Zynq TRM is very hard to follow. It doesn't have a proper register specification section, I had to deduct the registers and bit definitions from the text. I still find using Xilinx's BSP unconvenient, one has to follow the methods decided by Xilinx's engineers which are not so well documented in first place. If a design departs from the pre-written examples it is a challenge to understand how the APIs interoperate
  5. Same problem here, I have a Cora board and need to use the PS UART in interrupt mode to receive data. I use some sample code by Xilinx and from other Digilent projects but it doesn't work. Something I notice is that after I configure the UART and the GIC, I read the uart's IER and IDR registers, which should hold the enabled and disabled interrupt masks, and they are both 0. Furthermore, I tried to use XSCT to manually write them but they remain at 0. Either they are locker or, could it be, they don't exist because they must be enabled in the HW design. Yet I can't find any part of t
  6. @vicentiu I've marked your response as solution as it is the solution to my question. However I'd like to add that some repos, such as u-boot, are too old already, the builder fails in latest ubuntu or debian (using libssl 1.1, maybe there're more problems after this point). I haven't tried the linux repo but I'm afraid similar issues may arise Been Cora a new board customers expect Digilent to provide updated tools and more documentation resources.
  7. https://github.com/Digilent/linux-digilent https://github.com/Digilent/linux-Digilent-Dev
  8. Thanks for your answer. I found that Digilent's own github contains u-boot and linux and, according to the notes posted, they now support Cora Z7. This is great! Howeve when I try to build u-boot I get this KNOWN error: https://forums.xilinx.com/t5/Embedded-Linux/U-Boot-compile-error-dereferencing-pointer/td-p/794782 According to that forum, the issue happens when using the latest libssl (1.1.0). Would it be possible for Digilent to try and test with a system using the latest libssl and then fix this issue? For Linux I'm a little puzzled since there're 2 repositories i
  9. I think the Cora Z7 has landed ok in the community, I see many posts about it here, however, overall, there's very little information online, besides it seems all focus is on using Xilinx' Petalinux. Has anybody tried to build Linux for Cora Z7 using buildroot? I rather use open source and tools so it'd be great to have some support in this regards. Thanks
  10. I'm seeing the same issue with Vivado 2018.3 and even using the latest board files (from april 18th 2019). Has anybody from Digilent actually tried to resolve? any clues so we can may resolved it by ourselves?
  11. Hello, Vivado 2018.3 fails during Implementation with error: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (17) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 17 sites. Term: rgb_led_tri_i[0] Term: rgb_led_tri_i[1] Term: rgb_led_tri_i[2] Term: rgb_led_tri_i[3] Term: rgb_led_tri_i[4] Term: rgb_led_tri_i[5] Term: rgb_led_tri_i
  12. I got the Arty A7 board back in 2016 and got it with a voucher for 1 year of vivado updates, up to Vivado 2017.4. I've been using 2017.4 without problems all this time. The Arty A7 board seems to have been very successful for Digilent and Xilinx since they keep making accessories, upgrades and stuff from it. Even recently Arm opened the M1/M3 cores for use in FPGA, and they use the Arty board as reference/test board. However the feature requires Vivado 2018.2. I also got recently a Cora Z7 which also recommends to use 2018.2 (I'm using it with 2017.4 without problems too).
  13. I use the S3E Sample Pack board on a regular basis and found it really useful. It is great to implement glue logic for bigger projects, as a companion board to monitor or debug signals or to build tools and interfaces to help in demos. Most of the designs at my company use big expensive boards (e.g. virtex 7 vc707) which I don't like to carry with me when travelling or working remotely, having this little guy allows me to work, test and verify sections of my design remotely before implementing them on the bid guy. Having this board with picoblaze forms and ideal tool for many problems. Di
  14. Hey sLowe and [email protected], thanks a lot for your inputs, not only answered my questions but also gave me great advise. thanks again.
  15. Years ago I purchased my Atlys board. At that time I had ISE webpack already installed on my PC since I used it on my other boards and also all my designs were state machine based hence this setup was enough and I didn't bother much about license matters. Today I'm using more complex boards and ublaze extensively. However, it always comes very handy to use my old boards to test portions of my designs before moving to the big system. Specially since this allows me to work from home without having to carry the -very expensive- boards. However the XPS in the Ise webpack (14.7) does