ailee

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  1. Hi I'm need to write 1 byte of data to eeprom memory and struggling to find a working example, I read the data sheet but it leave more questions then it answers. Googled without too much luck. So may I tell you what I've think and maybe you would be kind enough to put me straight. I code below is the extract of my full code but its not working. Questions, 1) the Address, does this start a 0 or should it be a physical address? can't seem to find anything explaining this and whats is the physical address 2) I've see interrupts should be disabled, but others are say its not required? I'm thinking its dependant on how complex the interrupts are and times, but can not find a good explanation. 3) have I missed anything from the code below Many thanks Geoff /* Prototypes */ unsigned char eeprom_read(unsigned char address); void eeprom_write(unsigned char addreess, unsigned char value); /* Init the eeprom data area, only on byte is really needed */ __EEPROM_DATA(0xff,0,0,0,0,0,0,0); /* Define the variables */ volatile unsigned char EE_Value = 0xbb; unsigned char EE_Address = 0x00; /* Writing the flag to eeprom */ if (G12_Button_Changed == 1 && EE_Value != IH01_Button_Pressed) /* IH01 is 1 or 0 */ { EE_Value = IH01_Button_Pressed; EECON1bits.WREN = 1; eeprom_write(EE_Address, EE_Value); EECON1bits.WREN = 0; } #1
  2. I have a cheap Altera Cyclone II EP2C5T144C8 Dev Board and a few (4) of the IO/LVDS pins are shorted to VCC or GND as shown in the schematic segment below. The pins are also brought out to headers on the board. The only things I can think of for why they are there are: They are meant to be left non-populated (but were accidentally populated) for the user to add pull-up/pull-down resistors They are somehow helping power the FPGA Is there any reason a direct short to VCC/GND would be desirable for an IO pin on a Dev Board? Can I remove these resistors without negatively impacting the board's performance?
  3. MT9M001 is a CMOS image sensor. As its output it provides FRAME_VALID, LINE_VALID and DATA. The output signals are synchronized (edge-aligned) by PIXCLK, which is generated by the sensor. The datasheet is for example at http://www.kynix.com/Parts/4016034/MT9M001C12STM-DP.html I read the senosr output using FPGA, it somehow works, but I have a hard time understanding timing of LINE_VALID. Since this is the most critical signal for the image shape, I cannot ignore these problems anymore. The datasheet claims that the maximum frequency of the camera is 48MHz. This is the frequency I use, the period is 20.833. I am supposed to read at falling edge, which means at the 10.416 mark. This is a diagram from datahseet: To setup valid timing constrains, I have to focus on t_PLH and t_PLL. Let's see how they are defined (min, typical, max values): Acording to these data, LINE_VALID goes from low to high after up to 7 ns after rising edge of PIXCLK, which is at least 3.4 ns before falling edge (at 48MHz). This means t_LVS min value should be 3.4 ns, not 2 ns ...? But never mind, let's see t_PLL. Maximum value is 13 ns, which means LINE_VALID goes from high to low no later than 13 ns after PIXCLK rising edge. But PIXCLK falling edge happens 10.4 ns after PIXCLK rising edge, so LINE_VALID falling edge arrives later than PIXCLK falling edge. But only sometimes, because there is no typical or minimum value. Furthemore, if t_LVS is 2 ns, t_PLL would have to be lower or equal to 8 ns. How to handle this? For me it's a real problem, as my line lengths get messed up sometimes (especially when I overilluminate the camera). Based on t_OS and t_OH my data signal constraints are: create_clock -period 20.833 -name cam_pixclk [get_ports CAM_PIXCLK] create_clock -period 20.833 -name cam_pixclk_virt set_input_delay -min -1 -clock cam_pixclk_virt [get_ports CAM_DATA*] set_input_delay -max 1 -clock cam_pixclk_virt [get_ports CAM_DATA*] derive_pll_clocks derive_clock_uncertainty But how to continue with LINE_VALID?
  4. I would like to develop an application with Nordic's nRF8001 DevKit. The master emulator of this kit is an USB Dongle and it is originally meant for PC connection. My final goal for the project is to run it on an FPGA (possibly through Embedded Linux). Regarding this goal, I have some questions. 1) Is the master emulator (USB Dongle) compatible with Linux? Are there any open-source drivers or from Nordic? 1a) If there is a driver for Linux, can I use it with Embedded Linux or do I have to make some modifications to it? 1b) If there isn't a driver for Linux, can I write my own Embedded Linux driver (no prior experience on drivers)? Are there any similar/reference drivers? 2) Is it possible to use the nRF8001 chip, not the USB Dongle, with FPGA as a master, possibly through serial interface (SPI/UART)?
  5. I have a TLP521 driving a set of relays. The circuit is shown below. To switch on the relay, I will need to sink the current to complete the P521 circuit, which will trigger the relay. I am thinking to use a ULN2803A to sink the current as shown in the below diagram. This would mean that when I pull the Qa pin of shift register as HIGH, the 1C point (on ULN2803A) should be zero (grounded) and the circuit should be complete. Is this the correct way to do it? Please note that the common and gnd of ULN2803A are grounded and there is no +Vcc on the IC. Is this OK, or should I connect the COM to +5? (I don't want to source current to 1c by mistake or during initialization) Another question: Can I get rid of ULN2803 and directly sink the current from 595? I dont think it can sink this current.
  6. I have a need to connect an ARM micro-controller with 3.3V digital output pins to a few 12V solenoid water valves. I figured that I can use a ULN2803AP for this task. The internal circuit for each input/output is depicted below: Couple of questions: Is the attached schematic correct? Do I need anything else in the circuit to protect the micro-controller? Anything else needed to protect the ULN2803A? And do I tie the +12V and +5V grounds together? The load I'm driving is rated at about 400mA, 100mA shy of what this part is rated for ( each output ). The datasheet says the ULN2803AP can be put in parallel to handle more current. I'm mot sure how that circuit would look. Would I just logically connect them as if they are stacked one atop the other?
  7. It seems Arduino Due ( 32-bit, 84 Mhz, ARM-Cortex-M3-based SAM3X8E ) was released today. In addition, clearly there is a myriad of processors in this category ( 32-bit / 48-96 Mhz / ARM ) as well as corresponding prototyping boards: NXP LPC1768 / mBed STM32 / Discovery PIC32 / ChipKit PIC32 / Parallax Propeller LM4F120 / TI Launchpad etc. I am trying to understand the appeal of these "in-between" microprocessors, which to me appear to lie in between the low-end AVR/MSP430/etc. (pros: inexpensive, low-power, small-footprint) and the high-end ARM7/etc (pro: capable of far greater instructions per second). In what situations or ways are 32-bit / 48-96 Mhz / ARM-based microprocessors a suitable choice? More specifically, I am wondering in what applications or in which parameters they would make for a superior choice during design, over both the low-end 8-bit microcontrollers or the the very high-end ARM7 processors.