dnovick

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  1. Ah...thanks. I believe I tried both AC and DC coupling with no success, but I'll try again. Are a specific type of probes required or are there specific properties the probes need to have?
  2. Using Vivado with Anvyl board?

    Thanks for the quick response. ISE it is then!
  3. Using Vivado with Anvyl board?

    Good Day, I looked on the forum to see if this question was answered. While I saw hints to the answer, it wasn't clear. If this is a repeat, my apologies. I just purchased one of the Anvyl boards during the end of year sale. While I have ISE and Vivado both installed, I generally use Vivado only now for my Nexys4 DDR and ZedBoard, If possible, I'd like to use Vivado for designs on the Anvyl. Is this possible? If so, are their any Vivado board files available for this board (I searched but couldn't find any), or is it just a matter of me configuring the right FPGA and converting the info in the UCF file to a set of Vivado constraints? Thanks, Dave
  4. Sir, Sorry for the late reply. I just got a chance to go back and try it the way you described. I'm almost ashamed now, as once I tried it the way your picture depicts, it was as easy as can be. I thought for sure I had tried every possibility. Obviously not. Thanks much for the help. Hmmm...I actually like these a lot. I think I'll have to order another set or two for my son's AD2....the first set were for me. :-). Now I need to go back and figure out why the little BNC board I purchased from you to be able to use scope probes with the AD2 didn't work the first time I tried. I suspect it is once again, user error. Dave
  5. So, that's what I thought...and tried. I'm assuming that the metal pin inside the connector should make contact with the exposed part of the lead. Unfortunately, no matter how hard I jiggle, push, twist, and jump up and down, the lead will not go into the connector far enough to make contact and stay connected. I feel like this should be much easier than I'm finding it to be. I suspect the problem is me, but I just cannot figure this out. Dave
  6. I feel totally stupid, but am currently stumped. I've been using the Analog Discovery 2 for a while now. At the same time, I've had a set of the mini-grabbers that optionally go with it sitting around. I figured I'd hook 'em up today and start using them. Unfortunately, no matter what I try, I cannot figure out how to attach the probe wires to these mini grabbers. The only thing it says on the product page is that the probe contacts have to be facing outward. I've pushed, twisted, tried different angles to no avail. Does somebody have a picture they can upload that shows exactly how these buggers are supposed to be connected to the signal wires? Even a verbal explanation would help. http://store.digilentinc.com/mini-grabber-test-clips-6-pack-for-use-with-analog-discovery-flywires/ Thanks, Dave
  7. Good Day, I'm thinking of picking up the LabView Physical Computing kit that includes the Microchip PIC...i.e. the ChipKit WF32. I saw that there is a PMOD shield for the UNO standard, but it doesn't say specifically that it is supported on this ChipKit board. It only mentions some of the older boards. Does this shield work properly with this ChipKit? It would be great if it did, as I have a ton of PMODs that I bought for my Nexys4 DDR. My son would love to use them with ChipKit. Thanks, Dave
  8. Where is Vivado Design Suite Voucher?

    OK...that helps a lot. I just watched a training video from Zedboard.org which pointed out that the Design Edition came with the logic and serial analyzers. The fact that they now ship with the Webpack removes my concern that I may be missing something. I also was reading the Zed Board user guide and found that a license voucher for ChipScope Pro was supposed to be included. Has this also been superseded by the increased feature set of the Webpack version? Dave
  9. Where is Vivado Design Suite Voucher?

    So, I've been using the Webpack this PM, while waiting for an answer regarding my voucher. Of course, as you know, the Webpack is locked to only certain devices. However, the Zed Board is among those that are allowed. That said, I just took a look at the feature compare of the two versions, and they look exactly the same. That seems somewhat strange to me, as why would Xilinx sell licenses to a product equal to the free one? I guess maybe its just that the licensed version is not device limited. Of course, the voucher was also going to be device limited as well. If there are indeed no differences wrt the boards I'm using, I guess I'm ok. However, if there are any meaningful differences, I'd like to get the voucher. Thanks, Dave
  10. Good Day, I just purchased and received the Zed board from you folks. According to the product page, I'm supposed to have a voucher for one of the non-free versions of Vivado. Although the CD was shipped, I couldn't find a voucher. Where may I acquire it? Also, my understanding is that this license is device locked. So, I've been using Vivado free edition with my Nexys4 DDR. In order to keep using that board, am I going to need to have a separate install of Vivado - i.e. one free for my Nexys4 DDR and one for the Zed board? Thanks, Dave
  11. Problem with Using PMod IPs example project

    I believe I may have found the problem. If I run Vivado and the SDK in Administrator mode, the project gets created fine. This is similar to another issue I ran into on the first Microblaze project wherein the gcc exes don't work unless they are configured to run in Admin mode as well. Apparently, I must have run Vivado and the SDK in Admin mode when creating the first project.
  12. After successfully creating and running the Microblaze example project on my Nexys4DDR, I went on to create the project that walks through how to use the various Pmods. I followed the instructions carefully, and succesfully generate the bitstream and export the HW including bitstream. The SDK launches fine as well. However, when I go to create the new empty application, I receive the following error, "Project cannot be created. Reason: Internal error". When I click on "Details>>" I read the following: Internal Error: Failed to closesw "D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss" Reason: Cannot close sw design 'D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss'. Design is not opened in the current session. I notice first and foremost that the pmods_bsp directory doesn't exist under the IPMod1.sdk folder. Of course, this means also that none of the referenced files from that folder exist either. This would seem to be the root of the problem. However, I have no idea why this folder wasn't created nor how to resolve the issue. Any help is appreciated. Dave I also found the following in the SDK.log. I'm not sure if this helps. From what I can tell the generate_bsp process is failing. 11:42:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_standalone_v5_5::post_generate : couldn't execute "mb-ar": invalid argument while executing "exec $archiver -d $libgloss_a _interrupt_handler.o" (procedure "::sw_standalone_v5_5::post_generate" line 18) invoked from within "::sw_standalone_v5_5::post_generate standalone" 11:42:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1443] Error(s) while running TCL procedure post_generate() 11:42:18 ERROR : (XSDB Server)ERROR: [Hsi 55-1450] Error: running generate_bsp. 11:42:18 ERROR : Failed to closesw "D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss" Reason: Cannot close sw design 'D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss'. Design is not opened in the current session. 11:42:32 ERROR : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_standalone_v5_5::post_generate : couldn't execute "mb-ar": invalid argument while executing "exec $archiver -d $libgloss_a _interrupt_handler.o" (procedure "::sw_standalone_v5_5::post_generate" line 18) invoked from within "::sw_standalone_v5_5::post_generate standalone" 11:42:32 ERROR : (XSDB Server)ERROR: [Hsi 55-1443] Error(s) while running TCL procedure post_generate() 11:42:32 ERROR : (XSDB Server)ERROR: [Hsi 55-1450] Error: running generate_bsp. 11:42:32 ERROR : Failed to closesw "D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss" Reason: Cannot close sw design 'D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss'. Design is not opened in the current session. 11:42:56 ERROR : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_standalone_v5_5::post_generate : couldn't execute "mb-ar": invalid argument while executing "exec $archiver -d $libgloss_a _interrupt_handler.o" (procedure "::sw_standalone_v5_5::post_generate" line 18) invoked from within "::sw_standalone_v5_5::post_generate standalone" 11:42:56 ERROR : (XSDB Server)ERROR: [Hsi 55-1443] Error(s) while running TCL procedure post_generate() 11:42:56 ERROR : (XSDB Server)ERROR: [Hsi 55-1450] Error: running generate_bsp. 11:42:56 ERROR : Failed to closesw "D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss" Reason: Cannot close sw design 'D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss'. Design is not opened in the current session. 11:51:58 ERROR : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_standalone_v5_5::post_generate : couldn't execute "mb-ar": invalid argument while executing "exec $archiver -d $libgloss_a _interrupt_handler.o" (procedure "::sw_standalone_v5_5::post_generate" line 18) invoked from within "::sw_standalone_v5_5::post_generate standalone" 11:51:58 ERROR : (XSDB Server)ERROR: [Hsi 55-1443] Error(s) while running TCL procedure post_generate() 11:51:58 ERROR : (XSDB Server)ERROR: [Hsi 55-1450] Error: running generate_bsp. 11:51:58 ERROR : Failed to closesw "D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss" Reason: Cannot close sw design 'D:/Projects/FPGA/IPMod1/IPMod1.sdk/pmods_bsp/system.mss'. Design is not opened in the current session.