adacho94

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  1. Thanks, this link contains many valuable information, with examples similar to my question, for example always @(posedge CLK, posedge RST) if (RESET) Q <= 1'b0; else Q <= A | (B & C & D & E); The problem is, that I want to reset counter ONLY on the rising edge of x1. I think that when I use similar method to this example, counter can be reset on the rising edge of CLK when x1 is on high state.
  2. Hi, I have problems with my counter. Sorry for my poor english Register should be reset on the posedge of signal x1 and should be increased on the posedge of CLOCK. I know that register can be changed only in one always process, but I don't know how do that. The error is: Line 33: Signal register[11] in unit blagam_o_synteze is connected to following multiple drivers: blagam_o_synteze.v