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About Vonmuller

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  1. Hi Danny, Thank you for your positive review! To be honest, I completed this project almost 2 years ago and never came back to it ever since, so I actually do not remember much about what I was doing there :) This litlle project wasn't my main goal, I actually made it while waiting for the proper 16-bit data converters. It was kind of a warming up exercise. I do remember that making AD2 work was pain in the <moderated> and I do remember that datasheet wasn't really helpfull, so I understand your difficulties, but unfortunately I don't think I can help you here. Best r
  2. @[email protected], Yeah, I figured out how you did this, but I didn't try to do it myself yet. However, I have big plans for this stuff in the future, it will be useful in my area. ... and thank you for the references!
  3. @[email protected], Hell yeah! It would be interesting to try it! I've never heard or seen anything like this and, therefore, I didn't think it could be possible either. Now, having a live example in front of my eyes, I'll try to dig in this direction. It's not just for curiosity, it might be very useful in my research as well (not an FPGA implementation, but rather the mathematical way of approaching this problem). Thank you for sharing this!
  4. Hi @[email protected], Your solution looks very impressive, regardless of its implementation! I think this is a great achievement, DSP-wise, to make sidelobes as small as -60dB!!! I would be really curious to see what was the trick behind your solution from the math point of view, if are willing to share. Regards, Vonmuller
  5. Zygot, I hope so, that was the point!
  6. As I promised, design manual for the UDP echo-server project is ready. I uploaded it under the first post in this thread.
  7. A Belgian chocolate with red pepper, I guess But anyway, @zygot, I'll take my hat off to you, as you PHYNET project is much more complex than what I tried to do here! @[email protected] Thank you for your very much encouraging and kind words! To be honest, I don't think this project will get any further development. Only in case if I have any problems with data transmission in the future, I'll add TCP/IP protocol to it, but so far everything works great, so I don't want to spend any more time fixing the thing, which works (this echo-server, in fact, has already taken me much longer than I exp
  8. A few more words about the project I shared here with Digilent. The main purpose of it is to demonstrate implementation of Ethernet link between the PC and the Nexys 4 DDR board using VHDL. It is supposed to be a leg-up for the people who want to build their own Ethernet-based apps, but don't know where to start or have some difficulties with implementation. Working on this design, as a non-specialist in the PC communications' area, I found a few problems, partially related to incomplete/incorrect information in datasheets, partially - to the absence of comprehensive design guides relate
  9. @zygot, I'm glad you managed to explain yourself better this time and for the future make sure you adopt more polite tone, your condescension is not appreciated here. Also, note that making things yourself is always more beneficial than asking somebody to do something for you, especially if you don't know how to ask NICELY.
  10. I'm sorry, I didn't get this part about the udp_client.m code. What do you need it for?
  11. A UDP echo-server design uses on-board Ethernet port to create a data-link between FPGA board Nexys 4 DDR and MatLAB. Echo-server is capable of reception and transmission data packets using ARP and UDP/IP protocols. MAC address of FPGA board: 00:18:3e:01:ff:71 IP4 address of FPGA board: Port number of the board, used in the design, is 58210. The echo-server will reply back to any data server, which uses correct IP4 address and Port number of the board. MAC address of the board is made discoverable for the data server via ARP protocol. This echo-server design doesn't use
  12. Hi James, No problem, my pleasure! I hope it'll be useful! Best regards, Vonmuller
  13. Another set of figures show the result for UART core only, i.e. no data converters, UART Rx is connected to Tx directly in hardware. Command_vs_Feedback_(UART).tif Error_(UART).tif
  14. Figures below show performance results for the complete Function Generator block. Command_vs_Feedback_(FuncGen).tif Error_(FuncGen).tif Error_overlay_(FuncGen).tif
  15. This projects implements a custom function generator (FuncGen) implemented in VHDL on Nexys 4 DDR board using PmodDA4 and PmodAD2. Command signal to the function generator is supplied from Matlab through on-board UART bridge as a 16-bit long command word (unsigned integer). Digital command signal is converted into corresponding voltage signal by DAC (Pmod DA4), which can be used to drive external device. Feedback, implemented on the ADC (PmodAD2), allows user to read the actual level of the voltage signal. The feedback signal is sent back to the DTE (PC, Matlab), using the same UART bridge. No