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Posts posted by malkauns

  1. On 1/29/2020 at 6:02 AM, Cosmin said:

    Hello, malkauns.


    We built a small set of tools some time ago to handle dynamic generation and loading of bitstream files.

    Check it out at



    Thanks, I was able to create a bin file using "zynq" as the architecture argument.  Judging by the script its the only option anyway.  I'll try it out tonight on the hardware to see if it works.

  2. Ok, I know its been long but I'm finally resuming this project.  I generated a bitstream (.bit file) and want to create a .bin so that I can dynamically load it.  However, when trying to convert it to a .bin file I get the following error:


    /opt/pkg/petalinux/tools/hsm/bin/bootgen -image system_wrapper.bit -arch zynq -process_bitstream bin
    WARNING: bad character! '' (0x00)
    WARNING: bad character! '' (0x0F)
    WARNING: bad character! '�' (0xFFFFFFF0)
    WARNING: bad character! '' (0x0F)
    WARNING: bad character! '�' (0xFFFFFFF0)
    WARNING: bad character! '' (0x0F)
    WARNING: bad character! '�' (0xFFFFFFF0)
    WARNING: bad character! '' (0x0F)
    WARNING: bad character! '�' (0xFFFFFFF0)
    WARNING: bad character! '' (0x00)
    WARNING: bad character! '' (0x00)
    WARNING: bad character! '' (0x01)
    WARNING: bad character! '' (0x00)
    ERROR:BootGen - syntax error
       Line #1, "system_wrapper.bit".
    ... ���a0system_wrapper;UserID=0XFFFFFFFF;Version=2018.2b


    Please advise on how to properly convert from .bit to .bin.

  3. So it looks like /dev/xdevcfg is deprecated and /sys/class/fpga_manager/fpga0/firmware should be used instead.  However, after configuring Vivado to generate a .bin file I get the following error when trying to load the bitstream:

    [email protected]:~# cd /run/media/mmcblk0p2
    [email protected]:/run/media/mmcblk0p2# 
    [email protected]:/run/media/mmcblk0p2# mkdir /lib/firmware
    [email protected]:/run/media/mmcblk0p2# cp system_wrapper.bin /lib/firmware/
    [email protected]:/run/media/mmcblk0p2# echo system_wrapper.bin > /sys/class/fpga_manager/fpga0/firmware
    fpga_manager fpga0: writing system_wrapper.bin to Xilinx Zynq FPGA Manager
    fpga_manager fpga0: Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file
    fpga_manager fpga0: Error preparing FPGA for writing
    -sh: echo: write error: Invalid argument


    I read about using write_cfgmem to create a byte swapped bin file and tried the following TCL command in vivado:

    write_cfgmem -format bin -loadbit "up 0x0 /path/to/bit/file/system_wrapper.bit" out.bin 


    When trying to load the bitstream it results in the same error above.  How do I create a valid "byte swapped .bin file"?  Is there something wrong with my TCL command?

  4. I have a Zybo Z7 board I want to be able to dynamically load my .bit file after the system has booted.  I am using  In earlier versions I was able to do: cat file.bit > /dev/xdevcfg to have the bitstream loaded into the FPGA.  However, /dev/xdevcfg does not exist for me.  Is there something I have to configure when building the project and configuring the kernel to get this device to show up or is there some other way that I should be doing this?

  5.  I'm using Linux and am using this command to view output from the board:

    screen /dev/ttyUSB1 115200

    Using a BOOT.BIN and image.ub that I have made a while back I can get the board to complete the boot process and make it to the prompt so there must be something that needs tweaking in this project.  Is there some dtsi file that needs editing?  Maybe some boot option is missing.  Are you actually able the get this to boot on the Z7-10?


    Here's the boot log output where it gets stuck at "Starting kernel ...":

    U-Boot 2017.01 (Dec 18 2018 - 09:59:59 -0800)
    Model: Zynq Zybo Z7 Development Board
    Board: Xilinx Zynq
    I2C:   ready
    DRAM:  ECC disabled 1 GiB
    MMC:   [email protected]: 0 (SD)
    Using default environment
    In:    serial
    Out:   serial
    Err:   serial
    Net:   ZYNQ GEM: e000b000, phyaddr 1, interface rgmii-id
    SF: Detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, total 16 MiB
    Warning: [email protected] using MAC address from ROM
    eth0: [email protected]
    U-BOOT for Zybo Z7
    [email protected] Waiting for PHY auto negotiation to complete......... TIMEOUT !
    Hit any key to stop autoboot:  4  3  2  1  0 
    Device: [email protected]
    Manufacturer ID: 9f
    OEM: 5449
    Name: 00000 
    Tran Speed: 50000000
    Rd Block Len: 512
    SD version 3.0
    High Capacity: Yes
    Capacity: 7.4 GiB
    Bus Width: 4-bit
    Erase Group Size: 512 Bytes
    reading image.ub
    2281992 bytes read in 225 ms (9.7 MiB/s)
    ## Loading kernel from FIT Image at 10000000 ...
       Using '[email protected]' configuration
       Verifying Hash Integrity ... OK
       Trying '[email protected]' kernel subimage
         Description:  Linux Kernel
         Type:         Kernel Image
         Compression:  uncompressed
         Data Start:   0x100000d4
         Data Size:    2249752 Bytes = 2.1 MiB
         Architecture: ARM
         OS:           Linux
         Load Address: 0x00008000
         Entry Point:  0x00008000
         Hash algo:    sha1
         Hash value:   133089f2029c5e4eeeea23f7e95c11a63be240c3
       Verifying Hash Integrity ... sha1+ OK
    ## Loading fdt from FIT Image at 10000000 ...
       Using '[email protected]' configuration
       Trying '[email protected]' fdt subimage
         Description:  Flattened Device Tree blob
         Type:         Flat Device Tree
         Compression:  uncompressed
         Data Start:   0x102255e0
         Data Size:    30947 Bytes = 30.2 KiB
         Architecture: ARM
         Hash algo:    sha1
         Hash value:   399c9df8f6c14fe63d1e25f5d3e1786d61310363
       Verifying Hash Integrity ... sha1+ OK
       Booting using the fdt blob at 0x102255e0
       Loading Kernel Image ... OK
       Loading Device Tree to 07ff5000, end 07fff8e2 ... OK
    Starting kernel ...


  6. Hi Vicentiu,  Thanks for putting in the effort to make this work on the Z7-10.  I really appreciate what you all are doing.  However, I am unable to get the Z7 to boot fully.  It gets stuck at "Starting kernel".  Here are the commands I used to build Petalinux on a fresh install of Ubuntu 16.04 in VirtualBox:


    sudo apt-get update
    sudo apt-get install tofrodos gawk xvfb git libncurses5-dev tftpd zlib1g-dev zlib1g-dev:i386 libssl-dev flex bison chrpath socat autoconf libtool texinfo gcc-multilib libsdl1.2-dev libglib2.0-dev screen pax xterm python diffstat unzip libncurses-dev chrpath socat texinfo gcc-multilib libsdl1.2-dev
    sudo locale-gen en_US.UTF-8
    sudo dpkg-reconfigure locales #ok.. ok.. ok
    sudo apt-get install tftpd-hpa
    sudo chmod a+w /var/lib/tftpboot/
    sudo mkdir -p /opt/pkg/petalinux
    sudo chown $USER /opt/pkg/
    sudo chgrp $USER /opt/pkg/
    sudo chgrp $USER /opt/pkg/petalinux/
    sudo chown $USER /opt/pkg/petalinux/
    chmod +x
    ./ /opt/pkg/petalinux
    comment out the following line in /opt/pkg/petalinux/components/yocto/source/arm/layers/core/meta/conf/sanity.conf:
    INHERIT += "sanity" 
    git clone --recursive
    wget -O system.hdf
    mkdir system.hdf_zip
    unzip system.hdf -d system.hdf_zip
    cp -r system.hdf_zip/* Petalinux-Zybo-Z7-20/Zybo-Z7-20/project-spec/hw-description/ #i'm assuming this is where to magic is supposed to happen for the Z7-10..
    cp system.hdf Petalinux-Zybo-Z7-20/Zybo-Z7-20/project-spec/hw-description/ #..and here
    cd Petalinux-Zybo-Z7-20/Zybo-Z7-20/
    source /opt/pkg/petalinux/
    echo "configparams-sdk-launch-timeout 180" > .xsdbrc
    petalinux-package --boot --force --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system_wrapper.bit --u-boot
    cd images/linux
    cp BOOT.BIN image.ub /run/media/$USER/BOOT/
    sudo umount /dev/sdb2
    sudo dd if=rootfs.ext4 of=/dev/sdb2
    eject /dev/sdb
    #insert SD card into Zybo Z7-10, make sure its in SD boot mode and power on
    #hangs at "Starting kernel"


    Please let me know what I need to do to get it fully booting on the Z7-10.

  7. Hi all,  I am able to successfully build the PCAM demo project for the Zybo Z7-10 and can verify that it works.  After importing the project into the SDK and letting it build, sdk/pcam_vdma_hdmi/Debug/pcam_vdma_hdmi.elf is generated.  I would like to be able to run this application from with PetaLinux booted from an SD card so that I can control the camera as well as performing other operations within Linux.  If I try to run the generated pcam_vdma_hdmi.elf as it is I get an "Illegal instruction" error message.  What do I have to do to make this work from within a booted PetaLinux?

  8. Thanks for your reply.  I'm able to generate the bitstream for the Z7-10 after following your instructions.  However, isn't the debug module required to communicate with the logic running on the board so that I can set camera options (resolution etc.)?  After powering on the Zybo I am attaching to it over the serial port using screen /dev/ttyUSB1 115200 (on Linux).  When I program the board from Vivado I am expecting the camera options text to show up in the terminal so I can make selections.  In my case nothing shows up on the terminal.  Please tell me if I am making the wrong assumptions about how this is supposed to work.  My ultimate goal is to be able to send the sensor registers from Linux running on the PS to the camera sensor.


    error output:

    open_bd_design {/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/src/bd/system/}
    set_property PROBES.FILE {} [get_hw_devices xc7z010_1]
    set_property FULL_PROBES.FILE {} [get_hw_devices xc7z010_1]
    set_property PROGRAM.FILE {/home/<user>/Downloads/Zybo-Z7-20-pcam-5c-master/proj/pcam-5c.runs/impl_1/system_wrapper.bit} [get_hw_devices xc7z010_1]
    program_hw_devices [get_hw_devices xc7z010_1]
    INFO: [Labtools 27-3164] End of startup status: HIGH
    refresh_hw_device [lindex [get_hw_devices xc7z010_1] 0]
    INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
    WARNING: [Labtools 27-3361] The debug hub core was not detected.
    1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
    2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
    For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).


  9. I've tried implementing it for the Z7-10 but get the following error:

    [Place 30-487] The packing of instances into the device could not be obeyed. There are a total of 4400 slices in the pblock, of which 2903 slices are available, however, the unplaced instances require 3493 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced.
    Number of control sets and instances constrained to the design
    	Control sets: 808
    	Luts: 16409 (combined) 18202 (total), available capacity: 17600 
    	Flip flops: 18901, available capacity: 35200
    	NOTE: each slice can only accommodate 1 unique control set so FFs cannot be packed to fully fill every slice


    Critical warnings and error output:

  10. Ionut, thanks for your help.  I was able to generate the bitstream.   To note, I did have to "Reset Output Products" in order to get past a permissions error which according to the Xilinx forums occurs when the project is created on Vivado in Windows then implemented on Vivado on Linux.  It may be worth trying to address this issue if possible.  My next problem is that I encounter the following error when I try to program the device (Zybo Z7):


    ERROR: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device.
    ERROR: [Labtools 27-3165] End of startup status: LOW
    ERROR: [Common 17-39] 'program_hw_devices' failed due to earlier errors.


    In the project settings I have made sure that "Zybo Z7-20 (xc7z020clg400-1)" is the current selected "Project device".


    Full output:


    Please help and thanks for your help so far!

  11. I am using Vivado 2017.4 on Linux and am trying to build the pcam demo project.  The readme states "Created for Vivado 2017.4".  After downloading and extracting and I am executing the following steps:

    cp -r vivado-library-master/ip/* Zybo-Z7-20-pcam-5c-master/repo/vivado-library/
    <start vivado 2017.4 in tcl mode and cd to Zybo-Z7-20-pcam-5c-master/proj/>
    source create_project.tcl


    create_project.tcl produces the following output with error:

    ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-design '' is locked. Locked reason(s):
    * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. 
    List of locked IPs: 
    ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.
        while executing
    "make_wrapper -files [get_files $] -top -force"
        invoked from within
    "if {[llength $bd_list] != 0} {
      add_files -norecurse -quiet -fileset sources_1 [glob -nocomplain $src_dir/bd/*/*.bd]
      open_bd_design [glob -nocompla..."
        (file "create_project.tcl" line 123)


    Full output:


    When I try to implement I get the following error:

    [Place 30-569] BUFIO instance 'SerialClkBuffer' is driving 'I' pin of instance 'SerialClk_OBUF_inst'{OBUF}. This will lead to unroutable situation. A BUFIO can drive only clock pins of IO tile


    Can someone please point me in the right direction?


  12. I am having some trouble understanding how to do a simple data stream transfer from PL to PS.  I have memory mapped in the PS using /dev/mem where I will receive the data.  I am successful at achieving this but only for the first 32 bits of data.  I was hoping that there is some way to keep receiving data consecutively into the data buffer until tlast is issued on the PL side.  Maybe I am not understanding this correctly.

    Here is my design:


    Here is my ax_stream_test PL code:

    Here is my PS c code:

    The PS code is currently just a test project but eventually I will be transferring at least 3 megabytes per second from PL to PS.  If I am using the wrong IP's for this purpose then please suggest an alternative (but not BRAM because my final design is already using the maximum).  Thanks in advance for any help.

  13. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor.  The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer.  The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets.  In a small MIPI writeup located at there are 2 statements that are to be taken into consideration when trying to read data:

    "The high speed payload data from the transmitter is transmitted on both the edges of the High speed differential clock (DDR clock)"

    "The high speed differential clock and the data transmitted from the transmitter are 90 degrees out of phase and with the data being transmitted first."

    Using VHDL and Vivado, how do I create logic to successfully read data from this sensor?  I have the following code written (with notes/questions) but I'm pretty sure its wrong.  It was put together based on my limited understanding and reading various other source code that perform similarly:

    I was told that in order to derive the correct delay value I would have to sample the output clock at the rising edge. If it is not 1, decrement the delay value.  If it is 1, increment the delay value.  This way the delay should always be within +/- 1 of the ideal value.

    I have experimented with this code and tried to see how many SoT's I can detect but its very low (<10 per minute).  This is probably due to random chance. 

    Really need help on this one!

  14. I trying to use clock capable pin U15 on the Zynq using a Zybo board.  According to ug865-Zynq-7000-Pkg-Pinout.pdf U15 is one of the pins that are clock capable (MRCC/SRCC):


    However I am getting the "Poor placement for routing..." error suggesting that I use "CLOCK_DEDICATED_ROUTE FALSE" which states is undesirable.  Any idea what is going on here?  I'm trying to use this with a high speed camera interface.  thx

  15. Here is my system_top.dts that contains the gpio-keys device node:  My interrupt_v1_0 is connected exactly as shown in the first post.  I did try connecting the pulse signal directly to IRQ_F2P[0:0] on the zynq processing system.  This results in the system pausing while the interrupt is set high from the PL.  I modified my interrupt.vhd slightly:

            variable n : integer := 0;
            variable p : std_logic := '0';
            if rising_edge(CLK) then
                n := n + 1;
                if n = (100000000-1)/2 then
                    n := 0;
                    p := not p;
                end if;
            end if;
            pulse <= p;
    end process;

    serial input is halted for 1/2 second at a time.  However the int-test counter in /proc/interrupts still does not increment for any of the cpu's.

  16. Sorry for not getting back sooner.  I got side tracked with other aspects of my project.  The above solution of using a different linux code did not work.  However, cat /proc/interrupts looks like this once I load my driver and before loading my bit file:

               CPU0       CPU1       
     16:          0          0       GIC  27  gt
     17:          0          0       GIC  43  ttc_clockevent
     18:       1009       2507       GIC  29  twd
     21:         43          0       GIC  39  f8007100.adc
     61:          0          0  zynq-gpio  38  int-test
    141:          8          0       GIC  57  cdns-i2c
    142:          8          0       GIC  80  cdns-i2c

    I have it hooking (virtual interrupt??) 61 which should hook 29 (61-32).  Once I load my bitfile using: cat design_1_wrapper.bit > /dev/xdevcfg the interrupt counter for int-test does not increment as it should every second.  I think the driver side is correct as it shows up in the interrupts list but something is wrong on the PL side.  Oh, and once I load my bitfile I periodically get these messages:

    cdns-i2c e0005000.i2c: timeout waiting on completion
    cdns-i2c e0005000.i2c: timeout waiting on completion
    cdns-i2c e0005000.i2c: timeout waiting on completion
    cdns-i2c e0005000.i2c: timeout waiting on completion