malkauns

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Everything posted by malkauns

  1. Thanks, I was able to create a bin file using "zynq" as the architecture argument. Judging by the script its the only option anyway. I'll try it out tonight on the hardware to see if it works.
  2. Ok, I know its been long but I'm finally resuming this project. I generated a bitstream (.bit file) and want to create a .bin so that I can dynamically load it. However, when trying to convert it to a .bin file I get the following error: /opt/pkg/petalinux/tools/hsm/bin/bootgen -image system_wrapper.bit -arch zynq -process_bitstream bin WARNING: bad character! '' (0x00) WARNING: bad character! '' (0x0F) WARNING: bad character! '�' (0xFFFFFFF0) WARNING: bad character! '' (0x0F) WARNING: bad character! '�' (0xFFFFFFF0) WARNING: bad character! '' (0x0F) WARNING: bad character! '�' (0
  3. I can only get /dev/xdevcfg if I change "1496c680c6df2e3911feed13aa9663a851bf30e9" under Linux Components Selection -> Remote linux-kernel settings -> Remote Linux-kernel git TAG/Commit ID to "master". But then I lose /dev/media0 for the camera. Please advise.
  4. So it looks like /dev/xdevcfg is deprecated and /sys/class/fpga_manager/fpga0/firmware should be used instead. However, after configuring Vivado to generate a .bin file I get the following error when trying to load the bitstream: [email protected]:~# cd /run/media/mmcblk0p2 [email protected]:/run/media/mmcblk0p2# [email protected]:/run/media/mmcblk0p2# mkdir /lib/firmware [email protected]:/run/media/mmcblk0p2# cp system_wrapper.bin /lib/firmware/ [email protected]:/run/media/mmcblk0p2# echo system_wrapper.bin > /sys/class/fpga_manager/fpga0/firmware fpga_manager fpga0: writing system_wrapper.b
  5. I have a Zybo Z7 board I want to be able to dynamically load my .bit file after the system has booted. I am using petalinux-v2017.4-final-installer.run. In earlier versions I was able to do: cat file.bit > /dev/xdevcfg to have the bitstream loaded into the FPGA. However, /dev/xdevcfg does not exist for me. Is there something I have to configure when building the project and configuring the kernel to get this device to show up or is there some other way that I should be doing this?
  6. Thanks, I was able to get it to work after switching to initramfs. Really appreciate all your help!!
  7. I'm using Linux and am using this command to view output from the board: screen /dev/ttyUSB1 115200 Using a BOOT.BIN and image.ub that I have made a while back I can get the board to complete the boot process and make it to the prompt so there must be something that needs tweaking in this project. Is there some dtsi file that needs editing? Maybe some boot option is missing. Are you actually able the get this to boot on the Z7-10? Here's the boot log output where it gets stuck at "Starting kernel ...": U-Boot 2017.01 (Dec 18 2018 - 09:59:59 -0800) Model: Zynq Zybo
  8. Hi Vicentiu, Thanks for putting in the effort to make this work on the Z7-10. I really appreciate what you all are doing. However, I am unable to get the Z7 to boot fully. It gets stuck at "Starting kernel". Here are the commands I used to build Petalinux on a fresh install of Ubuntu 16.04 in VirtualBox: sudo apt-get update sudo apt-get install tofrodos gawk xvfb git libncurses5-dev tftpd zlib1g-dev zlib1g-dev:i386 libssl-dev flex bison chrpath socat autoconf libtool texinfo gcc-multilib libsdl1.2-dev libglib2.0-dev screen pax xterm python diffstat unzip libncurses-dev chrpath
  9. Thanks Jon. Hope to hear from someone soon.
  10. Hi all, I am able to successfully build the PCAM demo project for the Zybo Z7-10 and can verify that it works. After importing the project into the SDK and letting it build, sdk/pcam_vdma_hdmi/Debug/pcam_vdma_hdmi.elf is generated. I would like to be able to run this application from with PetaLinux booted from an SD card so that I can control the camera as well as performing other operations within Linux. If I try to run the generated pcam_vdma_hdmi.elf as it is I get an "Illegal instruction" error message. What do I have to do to make this work from within a booted PetaLinux?
  11. Thanks for all the help! With your instructions I was able to get the demo working on the Z7-10 board. Hopefully this thread will help others who run into similar issues.
  12. Ionut, thanks for helping me understand things better. After succesful implementation I followed your stage 1 and 2 instructions exactly but when I get to stage 3 I do not see "pcam_vdma_hdmi" anywhere when the SDK comes up. This is what the SDK window looks like: Please advise.
  13. Thanks for your reply. I'm able to generate the bitstream for the Z7-10 after following your instructions. However, isn't the debug module required to communicate with the logic running on the board so that I can set camera options (resolution etc.)? After powering on the Zybo I am attaching to it over the serial port using screen /dev/ttyUSB1 115200 (on Linux). When I program the board from Vivado I am expecting the camera options text to show up in the terminal so I can make selections. In my case nothing shows up on the terminal. Please tell me if I am making the wrong assumptions abo
  14. I've tried implementing it for the Z7-10 but get the following error: [Place 30-487] The packing of instances into the device could not be obeyed. There are a total of 4400 slices in the pblock, of which 2903 slices are available, however, the unplaced instances require 3493 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced. Number of control sets and instances constrained to the design Control sets: 808 Luts: 16409 (combined) 18202 (total), available capacity: 17600 Flip flops: 18901, available capacity: 35200 NOTE: each s
  15. OMG you're right, I have the Z7-10 not the Z7-20. I must have been half asleep. Will test again when i'm back home.
  16. Ionut, thanks for your help. I was able to generate the bitstream. To note, I did have to "Reset Output Products" in order to get past a permissions error which according to the Xilinx forums occurs when the project is created on Vivado in Windows then implemented on Vivado on Linux. It may be worth trying to address this issue if possible. My next problem is that I encounter the following error when I try to program the device (Zybo Z7): ERROR: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device. ERROR: [Labtools 27-3165] End of s
  17. I am using Vivado 2017.4 on Linux and am trying to build the pcam demo project. The readme states "Created for Vivado 2017.4". After downloading and extracting Zybo-Z7-20-pcam-5c-master.zip and vivado-library-master.zip I am executing the following steps: cp -r vivado-library-master/ip/* Zybo-Z7-20-pcam-5c-master/repo/vivado-library/ <start vivado 2017.4 in tcl mode and cd to Zybo-Z7-20-pcam-5c-master/proj/> source create_project.tcl create_project.tcl produces the following output with error: ERROR: [BD 41-1665] Unable to generate top-level wrapper HDL for the BD-des
  18. I am having some trouble understanding how to do a simple data stream transfer from PL to PS. I have memory mapped in the PS using /dev/mem where I will receive the data. I am successful at achieving this but only for the first 32 bits of data. I was hoping that there is some way to keep receiving data consecutively into the data buffer until tlast is issued on the PL side. Maybe I am not understanding this correctly. Here is my design: Here is my ax_stream_test PL code: https://pastebin.com/w1ZYbZwa Here is my PS c code: https://pastebin.com/rHze2HSz Th
  19. I'm trying to understand how to set up clocks and read data from a MIPI camera sensor. The sensor (Omnivision 5647) uses the MIPI CSI-2 protocol with D-PHY for the physical layer. The stage I am trying to get to is to be able to observer SoT (Start of Transmission) signals after which I can start parsing the CSI-2 protocol packets. In a small MIPI writeup located at http://archive.eetasia.com/www.eetasia.com/ART_8800715969_499489_TA_a466fca2_3.HTM there are 2 statements that are to be taken into consideration when trying to read data: "The high speed payload data from the transmitter i
  20. I trying to use clock capable pin U15 on the Zynq using a Zybo board. According to ug865-Zynq-7000-Pkg-Pinout.pdf U15 is one of the pins that are clock capable (MRCC/SRCC): However I am getting the "Poor placement for routing..." error suggesting that I use "CLOCK_DEDICATED_ROUTE FALSE" which states is undesirable. Any idea what is going on here? I'm trying to use this with a high speed camera interface. thx
  21. Here is my system_top.dts that contains the gpio-keys device node: http://pastebin.com/z8JLPLAC. My interrupt_v1_0 is connected exactly as shown in the first post. I did try connecting the pulse signal directly to IRQ_F2P[0:0] on the zynq processing system. This results in the system pausing while the interrupt is set high from the PL. I modified my interrupt.vhd slightly: process(CLK) variable n : integer := 0; variable p : std_logic := '0'; begin if rising_edge(CLK) then n := n + 1; if n = (100000000-1)/2 then
  22. Sorry for not getting back sooner. I got side tracked with other aspects of my project. The above solution of using a different linux code did not work. However, cat /proc/interrupts looks like this once I load my driver and before loading my bit file: CPU0 CPU1 16: 0 0 GIC 27 gt 17: 0 0 GIC 43 ttc_clockevent 18: 1009 2507 GIC 29 twd 21: 43 0 GIC 39 f8007100.adc 61: 0 0 zynq-gpio 38 int-test 141: 8 0 GIC 57 cdns-i2c