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  1. Hi Mikel, Dan thanks for the answers, I tried to use the same offset (0x00C00000) at first, and followed the tutorial steps.Triple checked that to make sure. Then tried other offsets , with the same result. No matter what, the bootloader hangs at the Xilsf initialize call. I did not modify the address map in Vivado. Dan, I tried to comment out the Xilsf line, and get another error from the bootloader, so I guess initialization is needed. I checked the linker script for both the bootloader and Hello_World apps. Both have only two sections : local_bram : Base : 0x50 , Size : 0x7FB0 . i
  2. Hi and thanks Dan &JColvin, I've been away from my Nexys DDR4 for a day (sigh). Just now,I tried the library patch approach suggested by Xilinx here. Result , the same , the bootloader hangs at the Xislf driver call. Dan the wrong memory map approach could make sense, I assume that the call to the Xilsf initialization is translated in an AXI access which might not reach the AXI Quad SPI slave. Any hints on what to check regarding the memory map definition? By the way , this is the Vivado System I am using: There both s_axi_clk and ext_spi_clk are tied to clk_out
  3. Ok, going on with the tutorial: I flashed the Quad SPI (the flashing screen capture has to be corrected to show the part ID: s25fl128sxxxxxx0) and reset the board. Teraterm shows SREC SPI Bootloader (first VERBOSE msg in bootloader app) an nothing else. If I set breakpoints in the bootloader code,I see that the following call is problematic: Status = XIsf_Initialize(&Isf, &Spi, ISF_SPI_SELECT, IsfWriteBuffer); This returns Status = 1, so I guess the bootloader exits here. Any hint what can go wrong? Z
  4. Yup:) But it might be harmless to post a blog with pictures of the off the shelf parts I will use and a description on how to use them. Also, a basic block diagram of the design in the Artix-7 can follow. But I'll guess I'll have to keep some tricks of the trade Still , the BOM for that project includes components such as expensive CHIRP sonar transducers, and can reach few thousand dollars, so I would not be doing this on my own without a business interest:)
  5. Hmmm..would lovely do it, but it is an industry project...so...
  6. Hi Dan! Ok, now I think I get (hard head here!), so I probably need an external dynamic memory for run time tasks of the CPU application. (could run in internal FPGA BRAM if extremely simple, right?) And for sure the 128 Mb DDR2 of the Nexys4 DDR gives for much more room than the required for the Hello World UART example. I want to use the Nexys4 DDR to prototype a final product, the FPGA part will need about 4 Mbyte of external RAM for temp FFT result storage. The SW application for the Ethernet communication and peripheral control is not clear for me by the time, but guess will be
  7. Hi Dan, I´m very happy to have purchased a Nexys4 DDR , and my goal is to prototype the core of a transceiver board for a sonar navigation echosounder. The FPGA will basically have a transmit stage,a receive stage , a housekeeping stage (plan to use the XADC there) and an command/status & data procotol over Ethernet. Thanls for the Wishbone lonk, I´ll have a look. By now , my immediate goal is to get familiar with the board by trying: 1- To access to separate memory areas defined in the FPGA. Maybe DPRAMs, or simple registers via the Ethernet link. I think I can modify the
  8. Hi Dan, Thanks for the feedback, my question is not about MIG and DDRs (I have used DDR2 ad DDR3 with the MIG in Virtex 4/5 and old ISE 13.1 CoreGen) , but I don´t see the need of a DDR for a bootloading task. I am a noob in embedded software, but should nt the Quad SPI Flash in the Nexys 4 DDR enough to allocate the program? Why is the DDR needed for application program at all?
  9. HI guys I want to introduce myself , since I feel I will be around for a while. I am an FPGA designer with about 10 years experience in RTL IP design (mostly in VHDL), mainly for mission critical applications. My work has been always designing and verifying interfaces for the front end, typically ADCs/DACs, DDR memories , audio/video processing and some communication. Now it is time for me to move to Vivado and go embedded, so I bought a Nexys DDR board for a project I m working in and want to experiment , mostly with microblaze. First thing I am trying is to configure the FPGA
  10. Hi, First of all , thanks to the digilent guys and all the users of the forums for the info provided here. I am a newbie to Microblaze, and Vivado , but experienced with ISE and traditional RTL design flow. I am just trying to cut my path down through some of the tutorials to see what I can use for a project I need to do. By now I am stuck with the "How To Store Your SDK ..." tutorial. Have a couple of questions: 1- I built the Microblaze system with the Quad SPI core mentioned in the intro and exported to SDK. When I generate the linker script of the "Hello World.c" , I see I s
  11. Hi jpeyron, Thanks for that, I just used the same settings for the Microblaze than in the Nexys4 tutorial and it worked.
  12. Forgot to add...I am using the Nexys4 DDR , not the Nexys4 , therefore I am following this tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start.
  13. Hi, I triple checked. All steps as in the tutorial, including Block automation for MIG IP before running Run Connection Automation. And still , the microblaze_0 checkbox is not there for me to uncheck, and after connection automation , the axi_mem_intercom block is missing. A side note, in order to get the microblaze_0_xlconcat & microblaze_0_axi_intc blocks you need to enable interrupts for the Microblaze (as obvious as it seems , it is ot stated in the tutorial). Is there any guru from digilent (maybe the author of the tutorial) available to help?
  14. By the way, I am using Vivado 2016.2 . Has this tutorial been implemented with versions later than 2015.1?
  15. apuchkov. I read that, my problem is that the microblaze_0 checkbox is not there, and I don't know why.