dnappier

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About dnappier

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  1. I'm trying to get started with a simple project on the NexysVideo where I simply pass the HDMI signal through. I created the following Block Design: The clocking wizard is supposed to be using the 100 external clock on the board. I am getting the following errors during implementation: [BD 41-1273] Error running apply_rule TCL procedure: can't read "board_if": no such variable ::xilinx.com_bd_rule_mig_7series::apply_rule Line 48 and [Place 30-149] Unroutable Placement! A MMCM / (BUFIO/BUFR) component pair is not placed in a routable site pair. The MMC
  2. I am trying to synthesize the GPIO demo for the NexysVideo and I am getting a synthesis error that I need some help with. The error is: <path>/NexysVideo/Projects/GPIO/src/ip/charLib/charLib.dcp is not a valid design checkpoint Has anyone else seen this and know how to fix this? I am using Vivado 2015.3 if that helps. I'm including a an image of the full output