I'm trying to get started with a simple project on the NexysVideo where I simply pass the HDMI signal through. I created the following Block Design:
The clocking wizard is supposed to be using the 100 external clock on the board.
I am getting the following errors during implementation:
[BD 41-1273] Error running apply_rule TCL procedure: can't read "board_if": no such variable
::xilinx.com_bd_rule_mig_7series::apply_rule Line 48
[Place 30-149] Unroutable Placement! A MMCM / (BUFIO/BUFR) component pair is not placed in a routable site pair. The MMCM component can use the dedicated path between the MMCM and the (BUFIO/BUFR) if both are placed in the same clock region or if they are placed in horizontally adjacent clock regions. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/I] >
hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X0Y3
hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/PixelClkBuffer (BUFR.I) is provisionally placed by clockplacer on BUFR_X0Y17
hdmi_i/dvi2rgb_0/U0/TMDS_ClockingX/SerialClkBuffer (BUFIO.I) is provisionally placed by clockplacer on BUFIO_X0Y16
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Does anyone have any ideas on how to fix this? It has been a long time since I have done FPGA design and I am very new to this block design methodology from Xilinx. Any help is appreciated.