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Everything posted by JerryG

  1. I can only surmise they do this as a result of an NDA with another party, or something similar, because I've reverse engineered the circuit on that part of the board and drawn the schematic and there's nothing special there at all--it's pretty much a bog standard implementation of what FTDI publishes on their site.
  2. You can just create an interface port for that pin. Edit the constraints file for your board and uncomment the line associated with L17 (and optionally rename the signal to something that makes sense to your project). Most of the Digilent-provided constraints files that I've seen define everything as LVCMOS33, which is fine for your purposes.
  3. JerryG

    Nexys A7-100

    Hi Sapna, Sounds like your board is faulty. I suggest contacting Digilent and see if any have any additional suggestions or if they want you to send the board back.
  4. Ah, yes, the infamous "This page intentionally left blank." page in the Arty schematic... This page is the interface between the FTDI chip used to implement the Jtag interface to the Artix FPGA. I'm not sure exactly what Digilent is trying to protect here as the schematic is pretty straightforward (I have a schematic for this section of the board. I didn't get it from Digilent--I beeped it out from a dead Arty board and drew the schematic myself). Please don't ask me for a copy--If Digilent doesn't want to give this info out, they must have their reasons and I'll respect that by not
  5. JerryG

    Nexys A7-100

    Does the board have power? Is LED "LD22" lit? The board can get power from the USB port, from a barrel connector, or from a battery/power supply connected to JP3/JP12. You need to make sure the jumpers are set correctly to correspond to the power source you're using. It's marked on the board's silkscreen, so it's easy to check and to set. Do you have the USB cable plugged into the "Prog/UART" USB port or the "USB Host" port? Your USB cable needs to be plugged into the "Prog/UART" port to supply power to the board and/or program the FPGA. Also, and this may be too obvious, so excuse m
  6. Why are all of these requests handled via PM? Why not just post the solution here for all to see and use?
  7. JerryG

    Arty Manual

    When will a full PDF manual for the Arty be available?
  8. Oh I agree 100%. Not publishing the entire schematic is just a cop-out in my opinion. I don't know what secrets Digilent/FTDI think they're keeping by not publishing an uncensored schematic, but it wouldn't be more than a minor inconvenience to a cloner. What it does accomplish, however, is deprive legitimate users of board information they might need.
  9. You'd have to sacrifice a board and remove all of the components. Blind and buried vias would be the next challenge, but not too difficult with a sacrificial board. The effort you put into it depends on how desperately you need to know the connections. Not publishing the full schematic is just a form of security by obscurity and will only hide the information from the unmotivated. People reverse engineer ICs all the time--that's much harder than reverse engineering a PCB.
  10. It wouldn't be hard to reverse engineer the connections for the FT2232 on the board if you really wanted to. All you have to do is trace the connections from the FT2232 pins to determine what they're connected to and draw your own schematic.
  11. JerryG

    PLL Clocks on Arty

    Anyone have or know of an example of how to configure a clock using a PLL on the Arty? I'd prefer a small, simple, example rather than some huge project involving MicroBlaze, etc.