Koss41

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  1. Koss41

    RAM write and read

    Im simulate this code in ModelSim.and I see very strange diagrams.I dont understand why signal q_b change like this
  2. Koss41

    RAM write and read

    hello, Could you pls help me/I have a problem with RAM dual port.My purpose is the write some data in this RAM on the certain addresses/like on the 1 and 16 address I want to put some data.and on the rest of the address will be zero data.I write code like library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity dp_ram_rbw_scl is generic ( DATA_WIDTH : integer := 8; ADDR_WIDTH : integer := 6 ); port ( -- common clock clk : in std_logic; -- Port A we_a : in std_logic; addr_a : in std_logic_vector(ADDR_WIDTH-1 downto 0);