InPhaseDesign

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  1. The PmodALS (and TI ADC081S021) work fine at 160kHz, at room temperature and with the Arty board USB powered. The sensor is very linear and stable.
  2. Thanks, BKallaher. Yes, I'll let you know. Obviously it pays to read the fine print. I was going by table 7.3 on page 4 of the TI datasheet 'recommended operating conditions.' At the top of the Electrical Characteristics Table 7.5 on pages 5 and 6, the note seems to say 1MHz to 4MHz for the "typical" values, which would imply the MAX/MIN spec limits should still be met over all the recommended operating conditions. However, note (3) (at the bottom) for the SCLK frequency range of 1MHz to 4MHz in this table says, "(3) This is the frequency range over which the electrical performance is ensu
  3. Hi, The reference manual for the PmodALS states, "The PmodALS requires the frequency of the SCLK to be between 1 MHz and 4 MHz." However, the TI ADC datasheet doesn't indicate any such restriction. It indicates the recommended SPI SCLK rate is from 25kHz to 20MHz. The PmodALS schematic appears to have direct wiring from the SCLK and SDATA pins to the PMOD connector, as well. What is the reason the PmodALS reference manual indicates a narrower range, especially a minimum of 1MHz? (A limited upper limit would be understandable for rise/fall time issues from trace capacitance, e
  4. @JerryG - Agreed, but that's way beyond reasonable effort for what should be a reference design (or for our project requirements). One would think the vendors would want designers to know how to user their parts... and if the board is doing something odd, they should at least help enlighten us. (I would note the far more complex AC701 board from Xilinx has complete schematics available, although it uses a different JTAG approach.) By the way, for this it's possible a board x-ray would be easier...
  5. Found it: From the Arty Reference web page there is a note about JP2 connecting the FT2232 BDBUS4 pin to the CK_RST line. BDBUS4 is controlled by the "B" port on the FT2232. When closing then reopening the COM/UART port this line toggles (drops low rapidly and slowly rises in about 3ms). In UART mode this pin is DTRn (data terminal ready bar), and it must be updated when the port is reopened. By disconnecting JP2 we break this connection to the FPGA and the reset from the FT2232 no longer causes the reset. @JerryG - "It wouldn't be hard to reverse engineer the connections ..." Tha
  6. Okay, thank you for the background. (Seems odd, but okay. Usually these boards are reference designs, as well, so the vendors would share the usage info.) A related question to the FT2232C on the Arty board: It appears that when I connect to ("open") the USB Serial Converter B port as a COM port from my PC that a reset is triggered at the FPGA, similar to clicking the red reset button, e.g. CK_RST on the schematics. Is this expected, and is there some way to disable that behavior? Since I can't see the wiring of the part it's a mystery... Thanks, Scott
  7. Hi, I'm new to the Arty7 board and the Artix 7, but have used FTDI 2232H's with several other FPGA boards in the past. It's quite a common part, and quite capable. I can't imagine what could possibly be proprietary about wiring up this part, as FTDI and every other board vendor out there provides complete schematics for their boards with this part. So, two questions: 1. Are you (Digilent) serious about this being a proprietary area of your board? I respectfully request you reconsider this in light of industry practice here. Some users like or need to dig into details to make the m