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Posts posted by omikron

  1. Hello

    I installed the newest Vivado 2016.2 and the newest Zybo board files from git repo.

    Any attemp to build the project ends with multiple Warnings during the place phase, saying that some Mio ports have more than one voltage standard. And the placement never ends.

    It happens even when I try the simplest BD with Zyng core and two AXI_GPIOs for leds and buttons.

    any idea?

  2. Hello

    I am using AXI_dynclk and rgb2dvi from Digilentic git. The ref clock od dynclk core comes to AXI_clk pin.

    When placing the design, I will always get this critical warning for each generated clock. And the design says Completed but timing constraints not met. How can I fix this?