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  1. Hello mskreen, Thanks for the response. I have given the pins numbers exactly as mentioned in the reference manual and schematic. I have snapshots of my constraints file and the details given in the reference manual in case you need to see them. I first generated the MIG IP core for a QDR controller and in the GUI the fixed pin out details had to be entered, upon which the IOSTANDARDS were automatically set (and they were the same as that given in the manual). However, when I set sys_rst to AA8 with IOSTANDARD LVCMOS18 I got the following error: [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 33. For example, the following two ports in this bank have conflicting VCCOs: qdriip_k_p (DIFF_HSTL_II, requiring VCCO=1.500) and sys_rst (LVCMOS18, requiring VCCO=1.800) I therefore changed the IOSTANDARD of sys_rst to HSTL_I and it worked fine. Later however, I had to use mdio and mdc pins at V13 and W13 to access the Management Interface of the Ethernet PHYs. Upon assigning them to the said pins with the IOSTANDARDS given in the manual, I got an error saying that the QDR read data pins in Bank 33 were assigned HSTL_I_DCI (which was what was given in the manual and also correctly taken by the MIG GUI) needed VRN and VRP pins of the bank 33 (which were V13 and W13) to be reference resistors but they were locked by mdc and mdio. So, I finally removed DCI and then it didn't throw the error. I have 2 questions: Is it alright to remove DCI from the QDR read data pins? Will the resulting loss in signal integrity be detrimental to system performance? If DCI should not be removed, what is a viable alternative? Thanks, Shashank.
  2. shashank0694


    Hi, I am working on NetFPGA 1G-CML featuring Kintex-7 (xc7k325tffg676). I am following the pin specifications given in the reference manuals, but during implementation on Vivado i get a "VCC Conflicts" due to "incompatible IOSTANDARDS" in the same bank. Could someone please advise me on why this happens or let me know where I could get the information? This is very important for me as it is happening in many cases and I am not able to decide which IOSTANDARD to use as I am a beginner in FPGAs. Moreover, in IO bank 32, the VRP and VRN pins are connected to mdc and mdio (Ethernet PHY Management interface) but there are QDR read data pins which need DCI due to which I get placement errors. If you wish to know the exact errors I would be happy to show them. If anyone has faced this problem before, I kindly request their guidance on this issue. Thanks
  3. Hi Mike, Thanks a lot for the reply. So, if the txc pin is an output, I take it that it does not need to be a Clock Capable pin? Also, which MAC core do you use/recommend? AXI Ethernet Lite is what I tried but that was before realising that it is not applicable for RGMII interface. Thanks
  4. Hi, I am working on NetFPGA - 1G CML board with Kintex-7 FPGA (xc7k325tffg676). The reference manual for the board specified a set of pin numbers for the 4 Ethernet PHYs on the board, which is shown in the image attached. However, when I synthesized and implemented a small test design which gives inputs to Ethernet Lite IP core to be transmitted across PHY, I got the following error during implementation: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets phy_tx_clk_IBUF] > phy_tx_clk_IBUF_inst (IBUF.O) is locked to IOB_X0Y214 and phy_tx_clk_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31 On posting a query on Xilinx forums, I was told that pin E13 is not a clock pin, whereas in the manual it is mentioned as phy_tx_clk. I was also directed to this link, which gives the package pin specifications by xilinx. All clock inputs should be given on Clock Capable (CC) pins indicated by SRCC or MRCC. However none of the 4 PHY transmit clocks (B9,D14,J10,E13) are CC pins. I checked the board schematic, but it is the same as the reference manual. I would be grateful to anyone who can guide me on what I should do to overcome this issue. Thanks.