shashank0694

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  1. Hello mskreen, Thanks for the response. I have given the pins numbers exactly as mentioned in the reference manual and schematic. I have snapshots of my constraints file and the details given in the reference manual in case you need to see them. I first generated the MIG IP core for a QDR controller and in the GUI the fixed pin out details had to be entered, upon which the IOSTANDARDS were automatically set (and they were the same as that given in the manual). However, when I set sys_rst to AA8 with IOSTANDARD LVCMOS18 I got the following error: [DRC 23-20] Rule violation (B
  2. Hi, I am working on NetFPGA 1G-CML featuring Kintex-7 (xc7k325tffg676). I am following the pin specifications given in the reference manuals, but during implementation on Vivado i get a "VCC Conflicts" due to "incompatible IOSTANDARDS" in the same bank. Could someone please advise me on why this happens or let me know where I could get the information? This is very important for me as it is happening in many cases and I am not able to decide which IOSTANDARD to use as I am a beginner in FPGAs. Moreover, in IO bank 32, the VRP and VRN pins are connected to mdc and mdio (Ethernet PHY M
  3. Hi Mike, Thanks a lot for the reply. So, if the txc pin is an output, I take it that it does not need to be a Clock Capable pin? Also, which MAC core do you use/recommend? AXI Ethernet Lite is what I tried but that was before realising that it is not applicable for RGMII interface. Thanks
  4. Hi, I am working on NetFPGA - 1G CML board with Kintex-7 FPGA (xc7k325tffg676). The reference manual for the board specified a set of pin numbers for the 4 Ethernet PHYs on the board, which is shown in the image attached. However, when I synthesized and implemented a small test design which gives inputs to Ethernet Lite IP core to be transmitted across PHY, I got the following error during implementation: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint