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  1. Thanks dan Whenever i run the simulation I'm getting this error very often. i could not solve it it please tell me where i made a mistake "Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings." here is the code i attached it bram1.coe mat_ply.vhd img1.vhd
  2. I tried it but i unable to resolve it..I'm getting this error [USF-XSim 62] 'compile' step failed with error(s) while executing 'C:/Users/ISRO/Desktop/FPGA/VHDL_CODING/SRIRAM/100_100_ram_writing/100_100_ram_writing.sim/sim_1/behav/compile.bat' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings. code.txt
  3. I unable to resolve the issue please kindly fix this if anyone had experience in this..... img.vhd mat_ply.vhd bram1.coe
  4. Do yu knw how to retrieve pixel from Block Rm?.....
  5. I'm having Genesys 2 Kintex 7 board.. i want to display image via VGA from block Ram. I stored pixel value (gray scale) in Block Ram and size of images is 100 * 100 and represent as 8 bits.. Is there is any example?? suggestion?
  6. can anyone tell me about how to display image from Block ram (gray scales pixels value) via VGA or HDMI?? Is there any working example ???

    1. Show previous comments  2 more
    2. hamster
    3. hilarikas


      Thanks a lot.....I'm appreciate your help..... But i need very specific.... Block ram to display  via HDMI and VGA or RAM to display image

      I have stored pixel values in BLOCK RAM by using core generator. I just want to display image from block ram...


      I'm execute this example and really thanks..It brings me some confidence

    4. hilarikas


      are you there?

  7. I'm really happy for you last post...you clear my doubts all thanks a lot..
  8. Thanks a lot for your valuable comment..I appreciate your help
  9. Hello Dan thanks for your reply... My board supports LVDS and clock frequency is about 200Mhz so i want to slow down as 1hz at 1 second... can you re write the prgram and also contraint ??
  10. yes I'm having difficulties in giving constraint file. Can you re write the VHDL program and constraint file according to genesys 2 Kintex 7..I just want to blink LED CLOCK DIVIDER (LED BLINKING).txt Genesys2_H.xdc
  11. Can anyone help me out I want to display simple image (200 x 200 gray scale image ) from FPGA ( Genesys 2 Kintex 7 ). I know the procedure how to give pixel values in RAM by coe.file But I don't know the procedure how to start ? where to find the procedure ? Which is one easy to display VGA Or HDMI? Is there any working example related to image display especially in Genesys 2