MartinBuk

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  1. Promlem solved :). I found this sentence in MIG datasheet "The LSBs of the AXI byte address are masked to 0, depending on the data width of the memory array. If the memory array is 64 bits (8 bytes) wide, AXI address[2:0] are ignored and treated as 0." I've used the first three bits as an address and it didn't work I'm gonna modify the code and share with you. Maybe it will be helpful for someone.
  2. I used switches because i work with them in previous project (like component). My solution is rather simple. I don't need debounce both way, because it has already built in this solution. I noticed that debounce filter has to be set for event about 1.2 ms long. It means that clock in process should be about 22KHz. process(CLK22KHZ) begin if rising_edge(CLK22KHZ) then but_buffer1 <= but_buffer1(39 downto 0) & INPUT(0); end if; end process OUTPUT(0) <= '1' when but_buffer1 = X"FFFFFFFFFF" else '0';
  3. yeah i've kind of done that. not with button but with switch. Loop isn't running over and over again, because it is checking actual and previous state on switches. if i decide to change adress or read/write mode, the loop will run again and stop. I think that was your point. or did i miss your idea? Martin
  4. You're right. i figured out, that address is the problem. i can't use the first three bits like an address. Rest works just fine. I don't know how is it so, but i can live with that. If you have any idea, let me know... thank you, Martin
  5. Maybe the issue is caused by IP implementation in my code. I set MIG by digilent and created own constraint file. As is shown below. Maybe MIG creates own constraint file as well. Do you know how IP core works? ##DDR2 SRAM set_property -dict { PACKAGE_PIN R7 IOSTANDARD SSTL18_II } [get_ports { ddr2_dq[0] }]; set_property -dict { PACKAGE_PIN V6 IOSTANDARD SSTL18_II } [get_ports { ddr2_dq[1] }];
  6. I've done this in different way. Maybe someone find it helpful. For example: if you put number 0.1100000000000000000000 it gives you "100011110000110100011000000" (75000000 dec). ----------------------------------float_to_bin--------------------------------------------- process(CLK100MHZ) variable sum : unsigned(49 downto 0) := (others => '0'); --0.50000000 --eight valid numbers ('0' & "5000 0000" & ---ZEROS---) constant const : unsigned(49 downto 0) := "01011111010111100001000000000000000000000000000000"; begin if rising_edge(CLK100MHZ) then for i in 0 to 22 loop if i = 0 then sum := (others => '0'); end if; if float_in(22-i) = '1' then --divide 50000000/2 in each interation --right shift register sum := sum + (const srl i); end if; end loop; --eight valid numbers bin_out <= sum(49 downto 23); end if; end process;
  7. There aren't any more meaningful logic circuits. In the final state(stWaitAct) of the state machine it is checking differences between actual and previous switch value. SWI is filtered output from physical switch. I wanted to avoid bouncing value. Maybe i would try to stretch de-bounce filter more. Request change between clock 1 and clock 3 could happen but it is unlikely. Because i was waiting to signal diode LED(15) in the final state.. process(sig_clk) begin if rising_edge(sig_clk) then if aState = stWaitAct then if adress /= SWI(15 downto 14) or comd /= ("00" & SWI(0)) then adress <= SWI(15 downto 14); comd <= ("00" & SWI(0)); ready <= '1'; else ready <= '0'; end if; end if; end if; end process; commnd <= "00" & SWI(0); LED(8 downto 1) <= data_out(7 downto 0);
  8. Which access do you mean? like Read, Read? If you mean access to data it shoul be feasible. Because i use switches and the state machine is waiting to my physical action. Should i use variables in different way? By the way thank you for your effort. i appreciate that.
  9. yeah, sorry for my english... The demo should somehow store data and be able to read them as well. for example (problem): i wrote data into address "001" and i could read them from same address. after that i was trying to wrote data into address "010" and i could read them as well but when i changed adress back to "001" in reading mode it was empty.
  10. no.. it was just for testing reason. That's demo where i want to verify the reading and writing into memory. in furture, i want to create data stream from camera.
  11. Hi guys, I've been working on implementation MIG into my project. I have a problem with write data into DDR2 (nexys 4ddr). Actually, it works but, if i want to write data into different address location. The previous one are lost. I can read and write data from the adress but i can't write data into an another addres and read both adress location. some how the previons data are lost. I will be very grateful for any help... process(sig_clk) begin if rising_edge(sig_clk) then case aState is when stInit => if sig_calib_complete = '1' then sig_en <= '0'; sig_wdf_wren <= '0'; sig_wdf_end <= '0'; --LED(15 downto 9) <= (others => '0'); if commnd = CMD_WRITE then aState <= stWriteComd; elsif commnd = CMD_READ then aState <= stReadComd; end if; end if; when stReadComd => sig_en <= '1'; sig_cmd <= CMD_READ; --LED(9) <= '1'; sig_addr(1 downto 0) <= SWI(15 downto 14); aState <= stComdAcep; when stWriteComd => sig_en <= '1'; sig_cmd <= CMD_WRITE; --LED(10) <= '1'; sig_addr(1 downto 0) <= SWI(15 downto 14); aState <= stComdAcep; when stComdAcep => if sig_rdy = '1' then sig_en <= '0'; --LED(12) <= '1'; if commnd = CMD_WRITE then sig_wdf_wren <= '1'; sig_wdf_end <= '0'; sig_wdf_data(12 downto 0) <= "1010101111111"; aState <= stWriteData; elsif commnd = CMD_READ then aState <= stWaitRead; end if; end if; when stWriteData => if sig_wdf_rdy = '1' then sig_wdf_wren <= '1'; sig_wdf_end <= '1'; --LED(13) <= '1'; sig_wdf_data(12 downto 0) <= "1010101010101"; aState <= stWaitAct; end if; when stWaitRead => if sig_rd_data_valid = '1' and sig_rd_data_end = '1' then --LED(14) <= '1'; aState <= stWaitAct; data_out <= sig_rd_data; end if; when stWaitAct => sig_wdf_wren <= '0'; sig_wdf_end <= '0'; --LED(15) <= '1'; if ready = '1' then aState <= stInit; end if; end case; end if; end process;
  12. Hi Guys I'm a student at technical university and i am interested in buying Nexys4 with academic discount. I read that academic verification is valid for 13 months. What does it mean for me? Can i buy a product with academic discount during 13 months or may i use that product only 13 months?