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About Natsu

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  1. Hello! I'm not trying to be an internet troll and perhaps I'm misunderstanding what you mean by satellite, but I suspect most of them are some expensive military grade processor that isn't very user friendly. This website seems to list some processors that have been used but it hasn't been updated in nearly 6 years... On the other hand though, what exactly does a satellite have to do with Digilent products considering this is on a Digilent forum instead of something like stackexchange or reddit? ~Natsu
  2. Hello! I'm by no means an expert or anything like that on oscilloscopes or software or drivers or anything like that, but it seems like there are a lot more threads on the WaveForms software than just this thread that seem to have been resolved successfully... and if you've given up and have no interest in seeing if anything has changed, why are you still here? Mostly I'm just a curious passerby. ~Natsu
  3. Hello, I don't have any technical advice to offer, but to a certain extent this conversation all seems like a problem with the Xilinx software experience since I don't think it's on Digilent to provide methods on what appears to be (from my inexperienced viewpoint) a non-standard use case. Or at least I presume Digilent isn't obligated to support non-GUI usage of Vivado. On another random side note, it may sometimes be a bit for Digilent to get responses from co-workers since there doesn't seem to be that many Digilent support people available to begin with, especially if it happens to be at the end of a business day with whatever time zone they are in. Just some random thoughts from a non-technical person who is probably wrong anyway. ~Natsu
  4. Hello! I don't know much about PWM or PDM, so maybe I've misinterpreted everything but I was under the impression that the blog post wasn't intended to be the ultimate solution for everything. I don't disagree that engineering should be replicated by other people to help ensure it all works rather than accepting stuff blindly, especially if it's vital for a projects success, but it looked like [email protected] was looking for better audio quality rather than launching rockets... On a different note, it looks like from his main blog page that [email protected] was at some conference these past few days so maybe he hasn't looked at this thread in the meantime? I'm just a little confused since it seems like you were aware of this in one of your posts with the "across the pond" statement but then proceeded to reply several more times with some apparent confusion as to why he hasn't responded. Then again, I'm neither [email protected] nor you nor a contributor for this Forum, so I'm probably just putting words in people's mouths. Sorry if I've offended anybody. ~Natsu
  5. Hello! I don't know the answer to your question at all, but if it's an option to you, it seems like a microcontroller based solution will be a lot easier to work with in terms of bit-banging SPI rather than working with Xilinx SDK which inherently has to use high level abstractions to control and rewrite the FPGA fabric to have it perform as you want it to. I'm guessing Digilent didn't create the SPI IP or the Microblaze, so I'm not sure anybody here on the forum could give you the internal details on how the IP works at a low level or what specific commands it uses; you'd probably have to ask on the Xilinx Forums for that since Xilinx made the IP. I'm sorry that I don't really have anything useful to offer you otherwise though. ~Natsu
  6. Hi! I don't have much in the way of useful advice to offer, but I'm thinking that the SEL pin can probably be left floating since it has a pull-up resistor to Vcc on it, at least according its schematic, so the IC5 is using that 20 Ohm resistor in what kinda looks like a differential amplifier in that lower right hand corner of the schematic. Setting SEL to ground would switch it so that the IC5 is using the 100 kOhm resistor, at least as far as I can tell. -Natsu
  7. Gotcha, that makes sense. I hadn't considered the fact that you would need hardware at least twice as fast as the signal of interest to nicely analyze it. I can still dream about it though at least. -Natsu
  8. @attila, Could the USB protocol become supported? I don't have a particular application in mind that I would use it for, and I imagine that it would be tricky to show nicely since I think USB tends to have some overhead in the datastream, but I think it would be super cool to tout that WaveForms 2015 can analyze USB -Natsu
  9. Hi Jon, I obviously haven't been back on here for awhile, but I did finally get that code working (after months of not looking at it). The problem I ended up having was I was having the LED output be based on the current LED state rather than the current switch state...XD. Since this nicely creates a recursive function (did I mention recursion?) or combinatorial loop in FPGA land, Vivado nicely decided to avoid letting me do that. Of course, the learn module based the outputs (leds) on the inputs (switches) and did not run into this problem...evidently I didn't actually read through example code to see that was the case. Next time I'll try to make sure that I actually read the answer before saying that it's wrong. Thanks for helping me out. Natsu
  10. Hi PaulStoffregen, I tried out your library from your github and didn't get any of the compilation errors you were mentioning. I wasn't sure how to specify path file within the .ino to make sure it linked to your library rather than the defaults, so I ended up deleting the Ethernet library folders from both the chipKIT core library set in AppData and the Arduino Ethernet library folder from the Program Files on my Windows 10 machine (since I figured I could always uninstall and re-download if something went drastically wrong). I am using the Arduino 1.6.13 ide and the chipKIT boards 1.3.1 version and compiled the WebClient example multiple times in a row for the random chipKIT boards I tested (Uno32, uC32, and WF32). I also tried the PachubeClientString example as a "random" other test, but with the same success as the WebClient example. I guess as a random side note, when I was on the chipKIT board 1.1.0 version, I always got a complaint about a yield function on all of the compilations, but I'm not seeing that anymore. Probably isn't helpful considering I didn't run into the error you're mentioning even though you are, but I figured I would share anyway. Thank you, Natsu
  11. Hi! I've been working on learning how to use FPGAs on my own and was feeling pretty good after finding a nice getting started guide for Vivado and some introductory projects using Verilog and successfully getting those projects to work on the Arty and even using some external IO with the Pmod ports since the Arty doesn't have all of the embedded switches and what not that some of the other Digilent boards seem to have. I'm using Vivado 2015.3 with the WebPack edition (maybe the Design Edition, I don't know if my voucher ran out yet or not). But my question is on the project 5 in the 4-bit shifter portion at the bottom (for both the ISE version and the Vivado version since it seems to be verilog based so it shouldn't really matter which one I use). I was feeling pretty brave and tried to do the project myself without looking at the provided code but kept getting a combinatorial loop error when I got to the bitstream generation portion, so I tried out the code that was provided in the project, but much to my surprise I received a combinatorial loop error too! Problem is, I don't really know what that means or how I might change the code so that it's less combining since it does a variety of inputs to make the shifter work... Basically, I'm at a loss as how to approach fixing this problem. I tried changing the sensitivity list in the always block (I think that's the right term) to just executing when I press the enable button (since that's the only time I'd want the shift to happen anyway), including all of the changing variables that Vivado suggested in the warnings created during synthesis, as well as just the variable used in the Project 5. I was really looking forward to trying out the other projects that are available but I figure I probably shouldn't try them until I get past the basics first. I'm not sure what all people might want to look at so I attached my verilog file, the XDC I modified from the "master" Arty xdc, and the error I'm getting. Here's the error: [DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop - 5 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. To allow bitstream creation for designs with combinatorial logic loops (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. led_OBUF[1]_inst_i_1, led_OBUF[1]_inst_i_2, led_OBUF[2]_inst_i_1, led_OBUF[3]_inst_i_2, led_OBUF[3]_inst_i_3. the top module: top.v and the xdc: Arty_Master.xdc Any advice on how to resolve this would be great. Thanks! Natsu
  12. Natsu


    Do you have a campfire that I could eat?
  13. Natsu

    photo album

    Lucy took all of the pictures