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About rappysaha

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  1. Hello @JColvin, Thank you for your reply. Can you please let me know about following question also: 1) HDMI IN and HDMI out interface in 5EV, will they have free IP support? Thank you
  2. You can use Xilinx frame buffer write ip in this purpose. You can save as many frame as possible within the capacity of your ddr3 memory.
  3. Hello, according to the image from GenesysZu-3eg, I can see a HDMI Tx and Rx interface. Can I solder a tx and Rx HDMI port according to the schematic and use this connection? Can I have this support from Digilent? Is there any established circuit connection or just the design? Since it is not sure when 5ev will release, this kind of support will be really helpful.
  4. Hello @elodg, Thank you for the reply. I have another questions. According to the Datasheet of Genesys Zu-3EG, "The Mini PCIe connector J13 doubles as an mSATA slot allowing fast non-volatile SSD storage. " If I connect an SSD via J13 connector, - By enabling, PCIe from MPSoc, what is the max read and write speed possible? - By enabling, SATA from MPSoc, what is the max read and write speed possible? I know speed will depend types of SSD. But is there any lab tested speed for any specific model? -Rappy
  5. Hello, How much DDR4 can I connect in Genesys Zu -3EG board? Is there any limit? Thank you
  6. Hello, Any latest update on a release date for the ZU-5EV board? Thank you
  7. Hi @[email protected], Thank you Dan. I will try to use the PLL feature. But, why PLL should have less jitter than MMCM? It will be helpful to me if I know the reason. I will be grateful to you. Rappy saha
  8. Hi @jpeyron, Thank you for your information. But, I have already fixed the clock pin H38(LA32_N) in my mezzanine board. I don't know how it will affect the clock. Any comment will be helpful. And I am also using the clock wizard IP and I am using "minimized jitter" option in Clock wizard IP. Is it the only way? Thank you Rappy Saha
  9. Hello everyone, I need suggestion about following topic: 1) I want to use an external oscillator 54 MHZ. And I want to take input this clock by FMC connector HA/LA pair (3.3 V) of genesys2 board. Is it will be ok? 2) The fixed oscillator 200 MHZ in Genesys2 is differential. I am producing my master clock for my design by MMCM. How can I have the minimum jitter? Any suggestion will be very helpful. Thank you Rappy Saha
  10. @JColvin Thank you very much. It was really helpful. I will try to collect further information from Xilinx forum.
  11. Hi @jpeyron, Thank you very much for your information. This is very helpful. If you may tell me about the differences between this license (OEM Kintex-7 FPGA XC7K325T Vivado Design Edition Voucher) and Vivado design edition voucher license (HL design edition). I will be very grateful if you may provide the information. Thank you Rappy saha
  12. Hello everyone, I need some information about Genesys2 Board license. When I have bought the genesys2 license, I get this license voucher: OEM Kintex-7 FPGA XC7K325T Vivado Design Edition Voucher. I want to know about following questions: is it a permanent license? Is there any time limit? Actually, I am confused with this information (bold and underlined): "The Genesys 2 is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE toolset, which includes ChipScope and EDK. Vivado comes with all the required cable drivers, so no separate
  13. Hi Testo, I don't know ZYNQ processor includes DDR3 or not but in my case, when I used Microblaze I added MIG IP to use DDR3. Thanks Rappy
  14. Hi Testo, I have initialized the VDMA with DDR3 and Microblaze processor. I don't know why you don't use DDR3 directly. I have a little knowledge about ZYNQ processor. What is the size of the malloc memory? Is it enough to hold your frame size? I am just asking because I am also working with same thing. Thanks Rappy Saha