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rappysaha last won the day on December 22 2016

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  1. Hi @[email protected], Thank you Dan. I will try to use the PLL feature. But, why PLL should have less jitter than MMCM? It will be helpful to me if I know the reason. I will be grateful to you. Rappy saha
  2. Hi @jpeyron, Thank you for your information. But, I have already fixed the clock pin H38(LA32_N) in my mezzanine board. I don't know how it will affect the clock. Any comment will be helpful. And I am also using the clock wizard IP and I am using "minimized jitter" option in Clock wizard IP. Is it the only way? Thank you Rappy Saha
  3. Hello everyone, I need suggestion about following topic: 1) I want to use an external oscillator 54 MHZ. And I want to take input this clock by FMC connector HA/LA pair (3.3 V) of genesys2 board. Is it will be ok? 2) The fixed oscillator 200 MHZ in Genesys2 is differential. I am producing my master clock for my design by MMCM. How can I have the minimum jitter? Any suggestion will be very helpful. Thank you Rappy Saha
  4. @JColvin Thank you very much. It was really helpful. I will try to collect further information from Xilinx forum.
  5. Hi @jpeyron, Thank you very much for your information. This is very helpful. If you may tell me about the differences between this license (OEM Kintex-7 FPGA XC7K325T Vivado Design Edition Voucher) and Vivado design edition voucher license (HL design edition). I will be very grateful if you may provide the information. Thank you Rappy saha
  6. Hello everyone, I need some information about Genesys2 Board license. When I have bought the genesys2 license, I get this license voucher: OEM Kintex-7 FPGA XC7K325T Vivado Design Edition Voucher. I want to know about following questions: is it a permanent license? Is there any time limit? Actually, I am confused with this information (bold and underlined): "The Genesys 2 is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE toolset, which includes ChipScope and EDK. Vivado comes with all the required cable drivers, so no separate installation is required. The free “WebPACK” versions of these toolsets do not support the Kintex-7 325T, however for a limited time a voucher with Design Edition will be included with no additional cost." I got this information from this link. Is it possible to generate the bit stream for any other target chips (other kintex or artix chips) with this license? Is it possible to generate an IP by HLS for any other target chips (other kintex or artix chips) with this license? Actually, I need to make sure about these issues very clearly. If I can't use this license for other chips, I may need buy license for other chips. Any suggestion will be very helpful. Thank you Rappy Saha
  7. Hi Testo, I don't know ZYNQ processor includes DDR3 or not but in my case, when I used Microblaze I added MIG IP to use DDR3. Thanks Rappy
  8. Hi Testo, I have initialized the VDMA with DDR3 and Microblaze processor. I don't know why you don't use DDR3 directly. I have a little knowledge about ZYNQ processor. What is the size of the malloc memory? Is it enough to hold your frame size? I am just asking because I am also working with same thing. Thanks Rappy Saha
  9. Hi @jpeyron, Thank you for your helpful assurance. I am eagerly waiting for the answer. Anyway I need to upload my SDK code to the flash. I am also trying by myself but I don't have any clue to go forward. Thank you Rappy Saha
  10. Hi @jpeyron, Thank you for answering back. With the SDK debugger (GDB) I also found same result. Without using SREC boot loader program the code for VDMA works fine. For VDMA, I am using the example code of Xilinx. Here I attached my code files. If you need anymore information to understand my problem please let me know. Any suggestion will be really helpful. Thanks Rappy Saha vdma.c vdma_api.c
  11. Hi, For my application, I am using VDMA IP. My project ran successfully without SREC bootloader program. But, when I am using SREC bootloader and trying to follow same procedure for SDK flash programming tutorial , I am having following error (Attached image). I am using flash image base addr= 0x00C00000. Why this kind error is happening? How can I handle this kind of error?? Any suggestion will be really helpful. Thank you Rappy Saha
  12. Hi, I still don't know why this kind (internal error : segmentation fault) of error is happening. But, when I tried the same procedure in new workspace, I overcame this kind of error. Rappy Saha
  13. Hi @jpeyron, Thank you. It is now very clear. I successfully generated the Hello World and download the whole SDK project into genesys2. It was ok. I was following this tutorial. I made an image processing Pipe with different image processing IP. I saw my download.bit file size is 4578 KB. I used bit compression. So, I used my "FLASH_IMAGE_BASE_ADDR" 0x0x004C4B40 = 5 MB. But, when I am going to use my own application, I faced some error. At step 2.2 of previously mentioned tutorial: - I tried to generate an "Empty application" and after hitting the finish button I am facing following error (attached image file 1st and 2nd). - I also attached my ADDRESS MAP of my project (attached image file 3rd). Why does this kind of error happen? How can I remove this error? Any suggestion will really helpful. Thank you Rappy saha
  14. Hi Mallesh, Currently they add a tutorial on resource page of Genesys2. You can follow that link. Otherwise you can also follow this thread. Rappy
  15. Hi everyone, Currently I am working with Genesys 2 board. My sensor output is 12-bit each component. My output design is attached below. I am using HDMI output. I collect the rgb2dvi IP form the "HDMI example". But the problem is that it only supports 8-bit input component. So, I have to convert output 12-bit component to 8-bit component at "AXI_video_out" IP. But, I think this type of convert mechanism degrading my output image quality. How can I convert the "vid_pData[23:0]" to "vid_pData[39:0]" at "rgb2dvi"? Any suggestion will be really helpful. Thanks Rappy