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  1. Scott, On page 6 of the ADC datasheet has the clock frequency between 1 and 4 MHz with a note that this is the range that electrical performance is ensured and a wider range is possible. Our ratings use this as a guide to guarantee that the device will work as expected. It should still work at the lower and higher frequencies. Let us know if you are able to get it working at these speeds. Regards, BKallaher
  2. Herrmattoon, source takes a bash script as an input not an executable. Here is some documentation for the source command: https://bash.cyberciti.biz/guide/Source_command So, to source Vivado the command is source /opt/Xilinx/Vivado/2015.4/settings64.sh And to source PetaLinux the command is source <PetaLinux Install Directory>/settings.sh Vivado and PetaLinux need to be the same version. So if you are running Vivado 2015.4, you need to be running PetaLinux 2015.4. Regards, BKallaher
  3. BKallaher

    JTAG HS3 Header

    Here is a right angle connector that should work with the HS3: http://www.digikey.com/product-detail/en/molex-llc/0878331420/WM18863-ND/662452. What sort of mechanical information are you looking for? BKallaher
  4. Those warnings can be safely ignored. Here is an explanation of what they mean: This is saying that the git archive command is not supported. The program then falls back to using git clone <repository> This says that webtalk was unable to communicate with the server. This is only so that Xilinx can track anonymous usage of their software. If you want to disable webtalk so you don't see the warning again fun this command: petalinux-util --webtalk off This last warning is just informing you that it will use the already cloned repository instead of
  5. I was able to recreate your problem. You should be using petalinux-v2015.4-final with that BSP. To fix the problem download and install Petalinux 2015.4 from here. Source the correct settings.sh. and run create, configure, and build again. BKallaher
  6. For that I would recommend the Nexys 4 DDR as the training modules were built around the Basys 3 and the Nexys 4 DDR. The Nexys Video is targeted for high speed audio/video applications and lacks some of the basic I/O used in the modules. BKallaher
  7. The main differences between the two are the available I/O and the size of the FPGA Device. So I can better help you, could you tell me what your target application is for the FPGA? BKallaher
  8. This may not be the cause of your problem but petalinux-build is know to fail if the correct 32-bit libraries are not installed. Try installing them with this command: sudo apt-get install lib32z1 lib32ncurses5 lib32bz2-1.0 lib32stdc++6 Hope this helps! BKallaher
  9. You are correct that the High-Speed Pmod ports are routed as differential pairs. If used in this way you need to ensure that shorts will not occur and that the voltage of the pins does not exceed 3.3 V (VCC on the Arty). Using the PmodRS485 in the manner that you describe will not work as the RX pin can not be driven by the device. If you want to work at higher line voltages I recommend obtaining a discrete RS422 transceiver connected to the High-Speed Pmod ports. BKallaher
  10. It seems that the links got moved to the reference manual for the Atlys. Here is the link: https://reference.digilentinc.com/reference/programmable-logic/atlys/reference-manual. The links are at the bottom of the page. BKallaher
  11. The WF32 has 2 UART Ports. UART1 is on pins 0 (RX) and 1 (TX) while UART4 is on pins 39 (RX) and 40 (TX). UART1 is also routed to the on-board FTDI chip so it cannot be used alongside the USB-UART bridge. For more information on the UART ports see the UART section of the WF32 reference manual. BKallaher
  12. BKallaher

    PLL Clocks on Arty

    I would recommend using the Clocking Wizard. This tool does not need to be used in a block design. Here is a PDF on the wizard: http://www.xilinx.com/support/documentation/ip_documentation/clk_wiz/v5_1/pg065-clk-wiz.pdf BKallaher
  13. BKallaher

    Cmod S6 toolchain?

    The Spartan 6 series is not supported by Vivado. The tool to use for the Spartan 6 is ISE. You can find the download for ISE at this link: http://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/design-tools.html BKallaher
  14. Unfortunately we cannot distribute the board layout due to the routing for the FTDI chip being proprietary. For differential pairing look at section 10.2 of the Arty Reference Manual. Two of the Pmod Headers are routed with impedance matched differential pairs for high speed routing. BKallaher
  15. There is a 3D STEP file available on the reference page for the Arty. BKallaher